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| WAN PLL IDT82V3255 Version 2 June 19, 2006 6024 Silver Creek Valley Road, San Jose, CA 95138 Telephone: (800) 345-7015 * TWX: 910-338-2070 * FAX: (408) 284-2775 Printed in U.S.A. (c) 2006 Integrated Device Technology, Inc. DISCLAIMER Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent, patent rights or other rights, of Integrated Device Technology, Inc. LIFE SUPPORT POLICY Integrated Device Technology's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the manufacturer and an officer of IDT. 1. Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any components of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Table of Contents FEATURES .............................................................................................................................................................................. 9 HIGHLIGHTS.................................................................................................................................................................................................... 9 MAIN FEATURES ............................................................................................................................................................................................ 9 OTHER FEATURES ......................................................................................................................................................................................... 9 APPLICATIONS....................................................................................................................................................................... 9 DESCRIPTION....................................................................................................................................................................... 10 FUNCTIONAL BLOCK DIAGRAM ........................................................................................................................................ 11 1 PIN ASSIGNMENT ........................................................................................................................................................... 12 2 PIN DESCRIPTION .......................................................................................................................................................... 13 3 FUNCTIONAL DESCRIPTION ......................................................................................................................................... 17 3.1 3.2 3.3 RESET ........................................................................................................................................................................................................... 17 MASTER CLOCK .......................................................................................................................................................................................... 17 INPUT CLOCKS & FRAME SYNC SIGNALS ............................................................................................................................................... 18 3.3.1 Input Clocks .................................................................................................................................................................................... 18 3.3.2 Frame SYNC Input Signals ............................................................................................................................................................ 18 3.4 INPUT CLOCK PRE-DIVIDER ...................................................................................................................................................................... 19 3.5 INPUT CLOCK QUALITY MONITORING ..................................................................................................................................................... 20 3.5.1 Activity Monitoring ......................................................................................................................................................................... 20 3.5.2 Frequency Monitoring ................................................................................................................................................................... 21 3.6 T0 / T4 DPLL INPUT CLOCK SELECTION .................................................................................................................................................. 22 3.6.1 External Fast Selection (T0 only) .................................................................................................................................................. 22 3.6.2 Forced Selection ............................................................................................................................................................................ 23 3.6.3 Automatic Selection ....................................................................................................................................................................... 23 3.7 SELECTED INPUT CLOCK MONITORING .................................................................................................................................................. 24 3.7.1 T0 / T4 DPLL Locking Detection ................................................................................................................................................... 24 3.7.1.1 Fast Loss .......................................................................................................................................................................... 24 3.7.1.2 Coarse Phase Loss .......................................................................................................................................................... 24 3.7.1.3 Fine Phase Loss ............................................................................................................................................................... 24 3.7.1.4 Hard Limit Exceeding ....................................................................................................................................................... 24 3.7.2 Locking Status ............................................................................................................................................................................... 24 3.7.3 Phase Lock Alarm (T0 only) .......................................................................................................................................................... 25 3.8 SELECTED INPUT CLOCK SWITCH ........................................................................................................................................................... 26 3.8.1 Input Clock Validity ........................................................................................................................................................................ 26 3.8.2 Selected Input Clock Switch ......................................................................................................................................................... 26 3.8.2.1 Revertive Switch ............................................................................................................................................................... 26 3.8.2.2 Non-Revertive Switch (T0 only) ........................................................................................................................................ 27 3.8.3 Selected / Qualified Input Clocks Indication ................................................................................................................................ 27 3.9 SELECTED INPUT CLOCK STATUS VS. DPLL OPERATING MODE ....................................................................................................... 28 3.9.1 T0 Selected Input Clock vs. DPLL Operating Mode .................................................................................................................... 28 3.9.2 T4 Selected Input Clock vs. DPLL Operating Mode .................................................................................................................... 30 3.10 T0 / T4 DPLL OPERATING MODE ............................................................................................................................................................... 31 3.10.1 T0 DPLL Operating Mode .............................................................................................................................................................. 31 3.10.1.1 Free-Run Mode ................................................................................................................................................................ 31 3.10.1.2 Pre-Locked Mode ............................................................................................................................................................. 31 3.10.1.3 Locked Mode .................................................................................................................................................................... 31 3.10.1.3.1 Temp-Holdover Mode .................................................................................................................................... 31 Table of Contents 3 June 19, 2006 IDT82V3255 WAN PLL 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.10.1.4 Lost-Phase Mode ............................................................................................................................................................. 31 3.10.1.5 Holdover Mode ................................................................................................................................................................. 31 3.10.1.5.1 Automatic Instantaneous ............................................................................................................................... 32 3.10.1.5.2 Automatic Slow Averaged ............................................................................................................................. 32 3.10.1.5.3 Automatic Fast Averaged .............................................................................................................................. 32 3.10.1.5.4 Manual ........................................................................................................................................................... 32 3.10.1.5.5 Holdover Frequency Offset Read .................................................................................................................. 32 3.10.1.6 Pre-Locked2 Mode ........................................................................................................................................................... 32 3.10.2 T4 DPLL Operating Mode .............................................................................................................................................................. 32 3.10.2.1 Free-Run Mode ................................................................................................................................................................ 32 3.10.2.2 Locked Mode .................................................................................................................................................................... 32 3.10.2.3 Holdover Mode ................................................................................................................................................................. 32 T0 / T4 DPLL OUTPUT ................................................................................................................................................................................. 34 3.11.1 PFD Output Limit ............................................................................................................................................................................ 34 3.11.2 Frequency Offset Limit .................................................................................................................................................................. 34 3.11.3 PBO (T0 only) ................................................................................................................................................................................. 34 3.11.4 Phase Offset Selection (T0 only) .................................................................................................................................................. 34 3.11.5 Four Paths of T0 / T4 DPLL Outputs ............................................................................................................................................. 34 3.11.5.1 T0 Path ............................................................................................................................................................................. 34 3.11.5.2 T4 Path ............................................................................................................................................................................. 35 T0 / T4 APLL ................................................................................................................................................................................................. 36 OUTPUT CLOCKS & FRAME SYNC SIGNALS ........................................................................................................................................... 36 3.13.1 Output Clocks ................................................................................................................................................................................. 36 3.13.2 Frame SYNC Output Signals ......................................................................................................................................................... 38 INTERRUPT SUMMARY ............................................................................................................................................................................... 40 T0 AND T4 SUMMARY ................................................................................................................................................................................. 40 POWER SUPPLY FILTERING TECHNIQUES ............................................................................................................................................. 41 LINE CARD APPLICATION .......................................................................................................................................................................... 42 4 MICROPROCESSOR INTERFACE .................................................................................................................................. 43 5 JTAG ................................................................................................................................................................................ 45 6 PROGRAMMING INFORMATION .................................................................................................................................... 46 6.1 6.2 REGISTER MAP ............................................................................................................................................................................................ 46 REGISTER DESCRIPTION ........................................................................................................................................................................... 51 6.2.1 Global Control Registers ............................................................................................................................................................... 51 6.2.2 Interrupt Registers ......................................................................................................................................................................... 58 6.2.3 Input Clock Frequency & Priority Configuration Registers ....................................................................................................... 62 6.2.4 Input Clock Quality Monitoring Configuration & Status Registers ........................................................................................... 73 6.2.5 T0 / T4 DPLL Input Clock Selection Registers ............................................................................................................................. 84 6.2.6 T0 / T4 DPLL State Machine Control Registers ........................................................................................................................... 88 6.2.7 T0 / T4 DPLL & APLL Configuration Registers ............................................................................................................................ 90 6.2.8 Output Configuration Registers .................................................................................................................................................. 103 6.2.9 PBO & Phase Offset Control Registers ...................................................................................................................................... 107 6.2.10 Synchronization Configuration Registers ................................................................................................................................. 109 JUNCTION TEMPERATURE ...................................................................................................................................................................... 111 EXAMPLE OF JUNCTION TEMPERATURE CALCULATION ................................................................................................................... 111 HEATSINK EVALUATION .......................................................................................................................................................................... 111 ABSOLUTE MAXIMUM RATING ................................................................................................................................................................ 112 RECOMMENDED OPERATION CONDITIONS .......................................................................................................................................... 112 I/O SPECIFICATIONS ................................................................................................................................................................................. 113 8.3.1 CMOS Input / Output Port ............................................................................................................................................................ 113 8.3.2 PECL / LVDS Input / Output Port ................................................................................................................................................ 114 7 THERMAL MANAGEMENT ........................................................................................................................................... 111 7.1 7.2 7.3 8.1 8.2 8.3 8 ELECTRICAL SPECIFICATIONS .................................................................................................................................. 112 Table of Contents 4 June 19, 2006 IDT82V3255 WAN PLL ORDERING INFORMATION .......................................................................................................................................... 127 8.4 8.5 8.6 8.7 8.3.2.1 PECL Input / Output Port ................................................................................................................................................ 114 8.3.2.2 LVDS Input / Output Port ................................................................................................................................................ 116 JITTER & WANDER PERFORMANCE ....................................................................................................................................................... 117 OUTPUT WANDER GENERATION ............................................................................................................................................................ 120 INPUT / OUTPUT CLOCK TIMING ............................................................................................................................................................. 121 OUTPUT CLOCK TIMING ........................................................................................................................................................................... 122 Table of Contents 5 June 19, 2006 List of Tables Table 1: Table 2: Table 3: Table 4: Table 5: Table 6: Table 7: Table 8: Table 9: Table 10: Table 11: Table 12: Table 13: Table 14: Table 15: Table 16: Table 17: Table 18: Table 19: Table 20: Table 21: Table 22: Table 23: Table 24: Table 25: Table 26: Table 27: Table 28: Table 29: Table 30: Table 31: Table 32: Table 33: Table 34: Table 35: Table 36: Table 37: Table 38: Table 39: Table 40: Table 41: Table 42: Table 43: Table 44: Table 45: Table 46: Table 47: Table 48: Pin Description ............................................................................................................................................................................................. 13 Related Bit / Register in Chapter 3.2 ........................................................................................................................................................... 17 Related Bit / Register in Chapter 3.3 ........................................................................................................................................................... 18 Related Bit / Register in Chapter 3.4 ........................................................................................................................................................... 19 Related Bit / Register in Chapter 3.5 ........................................................................................................................................................... 21 Input Clock Selection for T0 Path ................................................................................................................................................................ 22 Input Clock Selection for T4 Path ................................................................................................................................................................ 22 External Fast Selection ................................................................................................................................................................................ 22 `n' Assigned to the Input Clock ..................................................................................................................................................................... 23 Related Bit / Register in Chapter 3.6 ........................................................................................................................................................... 23 Coarse Phase Limit Programming (the selected input clock of 2 kHz, 4 kHz or 8 kHz) .............................................................................. 24 Coarse Phase Limit Programming (the selected input clock of other than 2 kHz, 4 kHz and 8 kHz) .......................................................... 24 Related Bit / Register in Chapter 3.7 ........................................................................................................................................................... 25 Conditions of Qualified Input Clocks Available for T0 & T4 Selection ......................................................................................................... 26 Related Bit / Register in Chapter 3.8 ........................................................................................................................................................... 27 T0 DPLL Operating Mode Control ............................................................................................................................................................... 28 T4 DPLL Operating Mode Control ............................................................................................................................................................... 30 Related Bit / Register in Chapter 3.9 ........................................................................................................................................................... 30 Frequency Offset Control in Temp-Holdover Mode ..................................................................................................................................... 31 Frequency Offset Control in Holdover Mode ............................................................................................................................................... 32 Holdover Frequency Offset Read ................................................................................................................................................................ 32 Related Bit / Register in Chapter 3.10 ......................................................................................................................................................... 33 Related Bit / Register in Chapter 3.11 ......................................................................................................................................................... 35 Related Bit / Register in Chapter 3.12 ......................................................................................................................................................... 36 Outputs on OUT1 & OUT2 if Derived from T0/T4 DPLL Outputs ................................................................................................................ 36 Outputs on OUT1 & OUT2 if Derived from T0/T4 APLL .............................................................................................................................. 37 Frame Sync Input Signal Selection .............................................................................................................................................................. 38 Synchronization Control ............................................................................................................................................................................... 38 Related Bit / Register in Chapter 3.13 ......................................................................................................................................................... 39 Related Bit / Register in Chapter 3.14 ......................................................................................................................................................... 40 Read Timing Characteristics in Serial Mode ................................................................................................................................................ 44 Write Timing Characteristics in Serial Mode ................................................................................................................................................ 44 JTAG Timing Characteristics ....................................................................................................................................................................... 45 Register List and Map .................................................................................................................................................................................. 46 Power Consumption and Maximum Junction Temperature ....................................................................................................................... 111 Thermal Data ............................................................................................................................................................................................. 111 Absolute Maximum Rating ......................................................................................................................................................................... 112 Recommended Operation Conditions ........................................................................................................................................................ 112 CMOS Input Port Electrical Characteristics ............................................................................................................................................... 113 CMOS Input Port with Internal Pull-Up Resistor Electrical Characteristics ................................................................................................ 113 CMOS Input Port with Internal Pull-Down Resistor Electrical Characteristics ........................................................................................... 113 CMOS Output Port Electrical Characteristics ............................................................................................................................................ 113 PECL Input / Output Port Electrical Characteristics ................................................................................................................................... 115 LVDS Input / Output Port Electrical Characteristics ................................................................................................................................... 116 Output Clock Jitter Generation .................................................................................................................................................................. 117 Output Clock Phase Noise ......................................................................................................................................................................... 118 Input Jitter Tolerance (155.52 MHz) .......................................................................................................................................................... 118 Input Jitter Tolerance (1.544 MHz) ............................................................................................................................................................ 118 List of Tables 6 June 19, 2006 IDT82V3255 WAN PLL Table 49: Table 50: Table 51: Table 52: Table 53: Table 54: Input Jitter Tolerance (2.048 MHz) ............................................................................................................................................................ Input Jitter Tolerance (8 kHz) .................................................................................................................................................................... T0 DPLL Jitter Transfer & Damping Factor ............................................................................................................................................... T4 DPLL Jitter Transfer & Damping Factor ............................................................................................................................................... Input/Output Clock Timing ........................................................................................................................................................................ Output Clock Timing .................................................................................................................................................................................. 118 118 119 119 121 122 List of Tables 7 June 19, 2006 List of Figures Figure 1. Functional Block Diagram ............................................................................................................................................................................ 11 Figure 2. Pin Assignment (Top View) .......................................................................................................................................................................... 12 Figure 3. Pre-Divider for An Input Clock ..................................................................................................................................................................... 19 Figure 4. Input Clock Activity Monitoring ..................................................................................................................................................................... 20 Figure 5. External Fast Selection ................................................................................................................................................................................ 22 Figure 6. T0 Selected Input Clock vs. DPLL Automatic Operating Mode ................................................................................................................... 29 Figure 7. T4 Selected Input Clock vs. DPLL Automatic Operating Mode ................................................................................................................... 30 Figure 8. On Target Frame Sync Input Signal Timing ................................................................................................................................................. 38 Figure 9. 0.5 UI Early Frame Sync Input Signal Timing .............................................................................................................................................. 38 Figure 10. 0.5 UI Late Frame Sync Input Signal Timing .............................................................................................................................................. 39 Figure 11. 1 UI Late Frame Sync Input Signal Timing ................................................................................................................................................. 39 Figure 12. IDT82V3255 Power Decoupling Scheme ................................................................................................................................................... 41 Figure 13. Line Card Application ................................................................................................................................................................................. 42 Figure 14. Serial Read Timing Diagram (CLKE Asserted Low) ................................................................................................................................... 43 Figure 15. Serial Read Timing Diagram (CLKE Asserted High) .................................................................................................................................. 43 Figure 16. Serial Write Timing Diagram ....................................................................................................................................................................... 44 Figure 17. JTAG Interface Timing Diagram ................................................................................................................................................................. 45 Figure 18. Recommended PECL Input Port Line Termination .................................................................................................................................. 114 Figure 19. Recommended PECL Output Port Line Termination ................................................................................................................................ 114 Figure 20. Recommended LVDS Input Port Line Termination .................................................................................................................................. 116 Figure 21. Recommended LVDS Output Port Line Termination ................................................................................................................................ 116 Figure 22. Output Wander Generation ...................................................................................................................................................................... 120 Figure 23. Input / Output Clock Timing ...................................................................................................................................................................... 121 List of Figures 8 June 19, 2006 WAN PLL IDT82V3255 FEATURES HIGHLIGHTS * The first single PLL chip: * Features 0.1 Hz to 560 Hz bandwidth * Exceeds GR-253-CORE (OC-12) and ITU-T G.813 (STM-16/ Option I) jitter generation requirements * Provides node clocks for Cellular and WLL base-station (GSM and 3G networks) * Provides clocks for DSL access concentrators (DSLAM), especially for Japan TCM-ISDN network timing based ADSL equipments Provides an integrated single-chip solution for Synchronous Equipment Timing Source, including Stratum 3, SMC, 4E and 4 clocks Employs DPLL and APLL to feature excellent jitter performance and minimize the number of the external components Integrates T0 DPLL and T4 DPLL; T4 DPLL locks independently or locks to T0 DPLL Supports Forced or Automatic operating mode switch controlled by an internal state machine; the primary operating modes are FreeRun, Locked and Holdover Supports programmable DPLL bandwidth (0.1 Hz to 560 Hz in 11 steps) and damping factor (1.2 to 20 in 5 steps) Supports 1.1X10-5 ppm absolute holdover accuracy and 4.4X10-8 ppm instantaneous holdover accuracy Supports PBO to minimize phase transients on T0 DPLL output to be no more than 0.61 ns Supports phase absorption when phase-time changes on T0 selected input clock are greater than a programmable limit over an interval of less than 0.1 seconds Supports programmable input-to-output phase offset adjustment Limits the phase and frequency offset of the outputs Supports manual and automatic selected input clock switch * * * * * * * * * * MAIN FEATURES * * * * * * * * * * * Supports automatic hitless selected input clock switch on clock failure Supports three types of input clock sources: recovered clock from STM-N or OC-n, PDH network synchronization timing and external synchronization reference timing Provides three 2 kHz, 4 kHz or 8 kHz frame sync input signals, and a 2 kHz and an 8 kHz frame sync output signals Provides 5 input clocks whose frequency cover from 2 kHz to 622.08 MHz Provides 2 output clocks whose frequency cover from 1 Hz to 622.08 MHz Provides output clocks for BITS, GPS, 3G, GSM, etc. Supports PECL/LVDS and CMOS input/output technologies Supports master clock calibration Supports Line Card application Meets Telcordia GR-1244-CORE, GR-253-CORE, ITU-T G.812, ITU-T G.813 and ITU-T G.783 criteria Serial microprocessor interface mode IEEE 1149.1 JTAG Boundary Scan Single 3.3 V operation with 5 V tolerant CMOS I/Os 64-pin TQFP package, Green package options available BITS / SSU SMC / SEC (SONET / SDH) DWDM cross-connect and transmission equipments Central Office Timing Source and Distribution Core and access IP switches / routers Gigabit and Terabit IP switches / routers IP and ATM core switches and access equipments Cellular and WLL base-station node clocks Broadband and multi-service access equipments Any other telecom equipments that need synchronous equipment system timing OTHER FEATURES * * * * * * * * * * * * * * APPLICATIONS IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. 9 2006 Integrated Device Technology, Inc. June 19, 2006 DSC-6773/2 IDT82V3255 WAN PLL DESCRIPTION The IDT82V3255 is an integrated, single-chip solution for the Synchronous Equipment Timing Source for Stratum 3, SMC, 4E and 4 clocks in SONET / SDH equipments, DWDM and Wireless base station, such as GSM, 3G, DSL concentrator, Router and Access Network applications. The device supports three types of input clock sources: recovered clock from STM-N or OC-n, PDH network synchronization timing and external synchronization reference timing. Based on ITU-T G.783 and Telcordia GR-253-CORE, the device consists of T0 and T4 paths. The T0 path is a high quality and highly configurable path to provide system clock for node timing synchronization within a SONET / SDH network. The T4 path is simpler and less configurable for equipment synchronization. The T4 path locks independently from the T0 path or locks to the T0 path. An input clock is automatically or manually selected for T0 and T4 each for DPLL locking. Both the T0 and T4 paths support three primary operating modes: Free-Run, Locked and Holdover. In Free-Run mode, the DPLL refers to the master clock. In Locked mode, the DPLL locks to the selected input clock. In Holdover mode, the DPLL resorts to the frequency data acquired in Locked mode. Whatever the operating mode is, the DPLL gives a stable performance without being affected by operating conditions or silicon process variations. If the DPLL outputs are processed by T0/T4 APLL, the outputs of the device will be in a better jitter/wander performance. The device provides programmable DPLL bandwidths: 0.1 Hz to 560 Hz in 11 steps and damping factors: 1.2 to 20 in 5 steps. Different settings cover all SONET / SDH clock synchronization requirements. A high stable input is required for the master clock in different applications. The master clock is used as a reference clock for all the internal circuits in the device. It can be calibrated within 741 ppm. All the read/write registers are accessed through a serial microprocessor interface. The device supports Serial microprocessor interface mode only. The device can be used typically in Line Card application. Description 10 June 19, 2006 IDT82V3255 T4 DPLL 77.76 MHz Functional Block Diagram GSM/GPS/16E1/16T1 T4 Input Selector MUX T4 PFD & LPF 16E1/16T1 Divider 12E1/24T1/E3/T3 10 OUT3 MUX Divider OUT1 Input Priority Priority Input Pre-Divider 10 T0 77.76 MHz Monitors T0 8 kHz 8 k Divider T4 APLL T4 APLL MUX FUNCTIONAL BLOCK DIAGRAM IN1_CMOS IN1_DIFF Priority Priority Input Pre-Divider OUT7 MUX Divider OUT2 EX_SYNC1 Input Pre-Divider Input Pre-Divider EX_SYNC1 IN2_CMOS IN2_DIFF EX_SYNC2 Priority EX_SYNC2 Input Pre-Divider 77.76 MHz IN3_CMOS EX_SYNC3 GSM/OBSAI/16E1/16T1 Figure 1. Functional Block Diagram 11 T0 APLL MUX PBO Phase Offset T0 Input Selector T0 PFD & LPF 12E1/24T1/E3/T3 16E1/16T1 Divider EX_SYNC3 T0 APLL Auto Divider Auto Divider FRSYNC_8K MFRSYNC_2K Output T0 DPLL APLL Microprocessor Interface JTAG June 19, 2006 OSCI WAN PLL IDT82V3255 WAN PLL 1 PIN ASSIGNMENT SONET/SDH IC8 IC7 IC6 IC5 IC4 AGND3 VDDA3 OUT2 IC3 VDDD6 DGND6 SDO TDI TDO TCK 64 63 62 AGND IC1 AGND1 VDDA1 INT_REQ OSCI DGND1 VDDD1 VDDD3 DGND3 DGND2 VDDD2 FF_SRCSW VDDA2 AGND2 IC2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 IDT82V3255 RST SCLK VDDD5 VDDD5 CS SDI CLKE TMS DGND5 VDDD5 VDDD5 TRST VDDD5 EX_SYNC3 IN3_CMOS EX_SYNC2 Pin Assignment FRSYNC_8K MFRSYNC_2K OUT1_POS OUT1_NEG GND_DIFF VDD_DIFF IN1_POS IN1_NEG IN2_POS IN2_NEG NC EX_SYNC1 IN1_CMOS IN2_CMOS DGND4 VDDD4 Figure 2. Pin Assignment (Top View) 12 June 19, 2006 IDT82V3255 WAN PLL 2 Name PIN DESCRIPTION Pin No. I/O Type Global Control Signal OSCI 6 I CMOS OSCI: Crystal Oscillator Master Clock A nominal 12.8000 MHz clock provided by a crystal oscillator is input on this pin. It is the master clock for the device. FF_SRCSW: External Fast Selection Enable During reset, this pin determines the default value of the EXT_SW bit (b4, 0BH) 2. The EXT_SW bit determines whether the External Fast Selection is enabled. High: The default value of the EXT_SW bit (b4, 0BH) is `1' (External Fast selection is enabled); Low: The default value of the EXT_SW bit (b4, 0BH) is `0' (External Fast selection is disabled). After reset, this pin selects an input clock pair for the T0 DPLL if the External Fast selection is enabled: High: Pair IN1_CMOS / IN1_DIFF is selected. Low: Pair IN2_CMOS / IN2_DIFF is selected. After reset, the input on this pin takes no effect if the External Fast selection is disabled. SONET/SDH: SONET / SDH Frequency Selection During reset, this pin determines the default value of the IN_SONET_SDH bit (b2, 09H): High: The default value of the IN_SONET_SDH bit is `1' (SONET); Low: The default value of the IN_SONET_SDH bit is `0' (SDH). After reset, the value on this pin takes no effect. RST: Reset A low pulse of at least 50 s on this pin resets the device. After this pin is high, the device will still be held in reset state for 500 ms (typical). EX_SYNC1: External Sync Input 1 A 2 kHz, 4 kHz or 8 kHz signal is input on this pin. EX_SYNC2: External Sync Input 2 A 2 kHz, 4 kHz or 8 kHz signal is input on this pin. EX_SYNC3: External Sync Input 3 A 2 kHz, 4 kHz or 8 kHz signal is input on this pin. Input Clock IN1_CMOS 29 I pull-down IN1_CMOS: Input Clock 1 A 2 kHz, 4 kHz, N x 8 kHz 3, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.48 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz or 155.52 MHz clock is input on this pin. IN2_CMOS: Input Clock 2 I CMOS A 2 kHz, 4 kHz, N x 8 kHz 3, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.48 MHz, 19.44 MHz, pull-down 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz or 155.52 MHz clock is input on this pin. IN1_POS / IN1_NEG: Positive / Negative Input Clock 1 A 2 kHz, 4 kHz, N x 8 kHz 3, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.48 MHz, 19.44 MHz, I PECL/LVDS 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz, 155.52 MHz, 311.04 MHz or 622.08 MHz clock is differentially input on this pair of pins. Whether the clock signal is PECL or LVDS is automatically detected. IN2_POS / IN2_NEG: Positive / Negative Input Clock 2 A 2 kHz, 4 kHz, N x 8 kHz 3, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.48 MHz, 19.44 MHz, I PECL/LVDS 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz, 155.52 MHz, 311.04 MHz or 622.08 MHz clock is differentially input on this pair of pins. Whether the clock signal is PECL or LVDS is automatically detected. CMOS Description 1 Table 1: Pin Description FF_SRCSW 13 I pull-down CMOS SONET/SDH 64 I pull-down CMOS RST 48 I pull-up CMOS Frame Synchronization Input Signal EX_SYNC1 EX_SYNC2 EX_SYNC3 28 33 35 I pull-down I pull-down I pull-down CMOS CMOS CMOS IN2_CMOS 30 IN1_POS IN1_NEG 23 24 IN2_POS IN2_NEG 25 26 Pin Description 13 June 19, 2006 IDT82V3255 WAN PLL Table 1: Pin Description (Continued) Name IN3_CMOS Pin No. 34 I/O I pull-down Type CMOS Description 1 IN3_CMOS: Input Clock 3 A 2 kHz, 4 kHz, N x 8 kHz 3, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.48 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz or 155.52 MHz clock is input on this pin. FRSYNC_8K: 8 kHz Frame Sync Output An 8 kHz signal is output on this pin. MFRSYNC_2K: 2 kHz Multiframe Sync Output A 2 kHz signal is output on this pin. Output Clock OUT1_POS OUT1_NEG 19 O 20 OUT1_POS / OUT1_NEG: Positive / Negative Output Clock 1 A 1 Hz, 400 Hz, 2 kHz, 8 kHz, 64 kHz, N x E1 4, N x T1 5, N x 13.0 MHz 6, N x 3.84 MHz 7, PECL/LVDS 5 MHz, 10 MHz, 20 MHz, E3, T3, 6.48 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz, 155.52 MHz, 311.04 MHz or 622.08 MHz clock is differentially output on this pair of pins. OUT2: Output Clock 2 A 1 Hz, 400 Hz, 2 kHz, 8 kHz, 64 kHz, N x E1 4, N x T1 5, N x 13.0 MHz 6, N x 3.84 MHz 7, CMOS 5 MHz, 10 MHz, 20 MHz, E3, T3, 6.48 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz or 155.52 MHz clock is output on this pin. Microprocessor Interface CS 44 I pull-up O CMOS CS: Chip Selection A transition from high to low must occur on this pin for each read or write operation and this pin should remain low until the operation is over. INT_REQ: Interrupt Request This pin is used as an interrupt request. The output characteristics are determined by the HZ_EN bit (b1, 0CH) and the INT_POL bit (b0, 0CH). SDI: Serial Data Input In Serial mode, this pin is used as the serial data input. Address and data on this pin are serially clocked into the device on the rising edge of SCLK. CLKE: SCLK Active Edge Selection In Serial mode, this pin selects the active edge of SCLK to update the SDO: High - The falling edge; Low - The rising edge. SDO: Serial Data Output In Serial mode, this pin is used as the serial data output. Data on this pin is serially clocked out of the device on the active edge of SCLK. SCLK: Shift Clock In Serial mode, a shift clock is input on this pin. Data on SDI is sampled by the device on the rising edge of SCLK. Data on SDO is updated on the active edge of SCLK. The active edge is determined by the CLKE. JTAG (per IEEE 1149.1) TRST 37 I pull-down I pull-up CMOS TRST: JTAG Test Reset (Active Low) A low signal on this pin resets the JTAG test port. This pin should be connected to ground when JTAG is not used. TMS: JTAG Test Mode Select The signal on this pin controls the JTAG test performance and is sampled on the rising edge of TCK. Output Frame Synchronization Signal FRSYNC_8K MFRSYNC_2K 17 18 O O CMOS CMOS OUT2 56 O INT_REQ 5 CMOS SDI CLKE 43 42 I pull-down CMOS SDO 52 I/O pull-down I pull-down CMOS SCLK 47 CMOS TMS 41 CMOS Pin Description 14 June 19, 2006 IDT82V3255 WAN PLL Table 1: Pin Description (Continued) Name Pin No. I/O I pull-down I pull-up Type Description 1 TCK: JTAG Test Clock The clock for the JTAG test is input on this pin. TDI and TMS are sampled on the rising edge of TCK and TDO is updated on the falling edge of TCK. If TCK is idle at a low level, all stored-state devices contained in the test logic will indefinitely retain their state. TDI: JTAG Test Data Input The test data is input on this pin. It is clocked into the device on the rising edge of TCK. TDO: JTAG Test Data Output The test data is output on this pin. It is clocked out of the device on the falling edge of TCK. TDO pin outputs a high impedance signal except during the process of data scanning. This pin can indicate the interrupt of T0 selected input clock fail, as determined by the LOS_FLAG_ON_TDO bit (b6, 0BH). Refer to Chapter 3.8.1 Input Clock Validity for details. Power & Ground VDDD1 VDDD2 VDDD3 VDDD4 VDDD5 VDDD6 VDDA1 VDDA2 VDDA3 VDD_DIFF DGND1 DGND2 DGND3 DGND4 DGND5 DGND6 AGND1 AGND2 AGND3 GND_DIFF AGND 8 12 9 Power 32 36, 38, 39, 45, 46 54 4 14 57 22 7 11 10 Ground 31 40 53 3 15 58 21 1 Ground Power VDDDn: 3.3 V Digital Power Supply Each VDDDn should be paralleled with ground through a 0.1 F capacitor. TCK 49 CMOS TDI 51 CMOS TDO 50 O CMOS VDDAn: 3.3 V Analog Power Supply Each VDDAn should be paralleled with ground through a 0.1 F capacitor. Power - VDD_DIFF: 3.3 V Power Supply for OUT1 DGNDn: Digital Ground AGNDn: Analog Ground Ground Ground - GND_DIFF: Ground for OUT1 AGND: Analog Ground Pin Description 15 June 19, 2006 IDT82V3255 WAN PLL Table 1: Pin Description (Continued) Name Pin No. I/O Type Others IC1 IC2 IC3 IC4 IC5 IC6 IC7 IC8 NC 2 16 55 59 60 61 62 63 27 IC: Internal Connected Internal Use. These pins should be left open for normal operation. Description 1 - - NC: Not Connected Note: 1. All the unused input pins should be connected to ground; the output of all the unused output pins are don't-care. 2. The contents in the brackets indicate the position of the register bit/bits. 3. N x 8 kHz: 1 < N < 19440. 4. N x E1: N = 1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64. 5. N x T1: N = 1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96. 6. N x 13.0 MHz: N = 1, 2, 4. 7. N x 3.84 MHz: N = 1, 2, 4, 8, 16, 10, 20, 40. Pin Description 16 June 19, 2006 IDT82V3255 WAN PLL 3 3.1 FUNCTIONAL DESCRIPTION RESET 3.2 MASTER CLOCK The reset operation resets all registers and state machines to their default value or status. After power on, the device must be reset for normal operation. For a complete reset, the RST pin must be asserted low for at least 50 s. After the RST pin is pulled high, the device will still be in reset state for 500 ms (typical). If the RST pin is held low continuously, the device remains in reset state. A nominal 12.8000 MHz clock, provided by a crystal oscillator, is input on the OSCI pin. This clock is provided for the device as a master clock. The master clock is used as a reference clock for all the internal circuits. A better active edge of the master clock is selected by the OSC_EDGE bit to improve jitter and wander performance. In fact, an offset from the nominal frequency may input on the OSCI pin. This offset can be compensated by setting the NOMINAL_FREQ_VALUE[23:0] bits. The calibration range is within 741 ppm. The performance of the master clock should meet GR-1244-CORE, GR-253-CORE, ITU-T G.812 and G.813 criteria. Table 2: Related Bit / Register in Chapter 3.2 Bit NOMINAL_FREQ_VALUE[23:0] OSC_EDGE Register NOMINAL_FREQ[23:16]_CNFG, NOMINAL_FREQ[15:8]_CNFG, NOMINAL_FREQ[7:0]_CNFG DIFFERENTIAL_IN_OUT_OSCI_CNFG Address (Hex) 06, 05, 04 0A Functional Description 17 June 19, 2006 IDT82V3255 WAN PLL 3.3 3.3.1 INPUT CLOCKS & FRAME SYNC SIGNALS INPUT CLOCKS Altogether 5 clocks and 3 frame sync signals are input to the device. The device provides 5 input clock ports. According to the input port technology, the input ports support the following technologies: * PECL/LVDS * CMOS According to the input clock source, the following clock sources are supported: * T1: Recovered clock from STM-N or OC-n * T2: PDH network synchronization timing * T3: External synchronization reference timing IN1_CMOS ~ IN3_CMOS support CMOS input signal only and the clock sources can be from T1, T2 or T3. IN1_DIFF and IN2_DIFF support PECL/LVDS input signal only and automatically detect whether the signal is PECL or LVDS. The clock sources can be from T1, T2 or T3. For SDH and SONET networks, the default frequency is different. SONET / SDH frequency selection is controlled by the IN_SONET_SDH bit. During reset, the default value of the IN_SONET_SDH bit is determined by the SONET/SDH pin: high for SONET and low for SDH. After reset, the input signal on the SONET/SDH pin takes no effect. 3.3.2 FRAME SYNC INPUT SIGNALS Three 2 kHz, 4 kHz or 8 kHz frame sync signals are input on the EX_SYNC1 to EX_SYNC3 pins respectively. They are CMOS inputs. The input frequency should match the setting in the SYNC_FREQ[1:0] bits. Only one of the three frame sync input signals is used for frame sync output signal synchronization. Refer to Chapter 3.13.2 Frame SYNC Output Signals for details. Table 3: Related Bit / Register in Chapter 3.3 Bit IN_SONET_SDH SYNC_FREQ[1:0] Register INPUT_MODE_CNFG Address (Hex) 09 Functional Description 18 June 19, 2006 IDT82V3255 WAN PLL 3.4 INPUT CLOCK PRE-DIVIDER Each input clock is assigned an internal Pre-Divider. The Pre-Divider is used to divide the clock frequency down to the DPLL required frequency, which is no more than 38.88 MHz. For each input clock, the DPLL required frequency is set by the corresponding IN_FREQ[3:0] bits. If the input clock is of 2 kHz, 4 kHz or 8 kHz, the Pre-Divider is bypassed automatically and the corresponding IN_FREQ[3:0] bits should be set to match the input frequency; the input clock can be inverted, as determined by the IN_2K_4K_8K_INV bit. Each Pre-Divider consists of a HF (High Frequency) Divider (only available for IN1_DIFF and IN2_DIFF), a DivN Divider and a Lock 8k Divider, as shown in Figure 3. The HF Divider, which is only available for IN1_DIFF and IN2_DIFF, should be used when the input clock is higher than (>) 155.52 MHz. The input clock can be divided by 4, 5 or can bypass the HF Divider, as determined by the IN1_DIFF_DIV[1:0]/IN2_DIFF_DIV[1:0] bits correspondingly. Either the DivN Divider or the Lock 8k Divider can be used or both can be bypassed, as determined by the DIRECT_DIV bit and the LOCK_8K bit. When the DivN Divider is used, the division factor setting should observe the following order: 1. Select an input clock by the PRE_DIV_CH_VALUE[3:0] bits; 2. Write the lower eight bits of the division factor to the PRE_DIVN_VALUE[7:0] bits; 3. Write the higher eight bits of the division factor to the PRE_DIVN_VALUE[14:8] bits. Pre-Divider IN1_DIFF_DIV[1:0] bits / IN2_DIFF_DIV[1:0] bits input clock HF Divider (for IN1_DIFF & IN2_DIFF only) Once the division factor is set for the input clock selected by the PRE_DIV_CH_VALUE[3:0] bits, it is valid until a different division factor is set for the same input clock. The division factor is calculated as follows: Division Factor = (the frequency of the clock input to the DivN Divider / the frequency of the DPLL required clock set by the IN_FREQ[3:0] bits) - 1 The DivN Divider can only divide the input clock whose frequency is lower than (<) 155.52 MHz. When the Lock 8k Divider is used, the input clock is divided down to 8 kHz automatically. The Pre-Divider configuration and the division factor setting depend on the input clock on one of the clock input pin and the DPLL required clock. Here is an example: The input clock on the IN2_DIFF pin is 622.08 MHz; the DPLL required clock is 6.48 MHz by programming the IN_FREQ[3:0] bits of register IN2_DIFF to `0010'. Do the following step by step to divide the input clock: 1. Use the HF Divider to divide the clock down to 155.52 MHz: 622.08 / 155.52 = 4, so set the IN2_DIFF_DIV[1:0] bits to `01'; 2. Use the DivN Divider to divide the clock down to 6.48 MHz: Set the PRE_DIV_CH_VALUE[3:0] bits to `0110'; Set the DIRECT_DIV bit in Register IN2_DIFF_CNFG to `1' and the LOCK_8K bit in Register IN2_DIFF_CNFG to `0'; 155.52 / 6.48 = 24; 24 - 1 = 23, so set the PRE_DIVN_VALUE[14:0] bits to `10111'. DIRECT_DIV bit LOCK_8K bit DivN Divider Lock 8k Divider DPLL required clock Figure 3. Pre-Divider for An Input Clock Table 4: Related Bit / Register in Chapter 3.4 Bit IN1_DIFF_DIV[1:0] IN2_DIFF_DIV[1:0] IN_FREQ[3:0] DIRECT_DIV LOCK_8K IN_2K_4K_8K_INV PRE_DIV_CH_VALUE[3:0] PRE_DIVN_VALUE[14:0] Register IN1_DIFF_IN2_DIFF_HF_DIV_CNFG IN1_CMOS_CNFG, IN2_CMOS_CNFG, IN1_DIFF_CNFG, IN2_DIFF_CNFG, IN3_CNFG FR_MFR_SYNC_CNFG PRE_DIV_CH_CNFG PRE_DIVN[14:8]_CNFG, PRE_DIVN[7:0]_CNFG Address (Hex) 18 16, 17, 19, 1A, 1D 74 23 25, 24 Functional Description 19 June 19, 2006 IDT82V3255 WAN PLL 3.5 INPUT CLOCK QUALITY MONITORING The qualities of all the input clocks are always monitored in the following aspects: * Activity * Frequency The qualified clocks are available for T0/T4 DPLL selection. The T0 and T4 selected input clocks have to be monitored further. Refer to Chapter 3.7 Selected Input Clock Monitoring for details. 3.5.1 ACTIVITY MONITORING Activity is monitored by using an internal leaky bucket accumulator, as shown in Figure 4. Each input clock is assigned an internal leaky bucket accumulator. The input clock is monitored for each period of 128 ms and the internal leaky bucket accumulator increases by 1 when an event is detected; it decreases by 1 if no event is detected within the period set by the decay rate. The event is that an input clock drifts outside (>) 500 ppm with respect to the master clock within a 128 ms period. There are four configurations (0 - 3) for a leaky bucket accumulator. The leaky bucket configuration for an input clock is selected by the cor- responding BUCKET_SEL[1:0] bits. Each leaky bucket configuration consists of four elements: upper threshold, lower threshold, bucket size and decay rate. The bucket size is the capability of the accumulator. If the number of the accumulated events reach the bucket size, the accumulator will stop increasing even if further events are detected. The upper threshold is a point above which a no-activity alarm is raised. The lower threshold is a point below which the no-activity alarm is cleared. The decay rate is a certain period during which the accumulator decreases by 1 if no event is detected. The leaky bucket configuration is programmed by one of four groups of register bits: the BUCKET_SIZE_n_DATA[7:0] bits, the UPPER_ THRESHOLD_n_DATA[7:0] bits, the LOWER_THRESHOLD_n_ DATA[7:0] bits and the DECAY_RATE_n_DATA[1:0] bits respectively; `n' is 0 ~ 3. The no-activity alarm status of the input clock is indicated by the INn_CMOS_NO_ACTIVITY_ALARM bit (n = 1, 2, or 3) / INn_DIFF_NO_ACTIVITY_ALARM bit (n = 1 or 2). The input clock with a no-activity alarm is disqualified for clock selection for T0/T4 DPLL. clock signal with no event clock signal with events Input Clock Decay Rate Leaky Bucket Accumulator Bucket Size Upper Threshold Lower Threshold 0 No-activity Alarm Indication Figure 4. Input Clock Activity Monitoring Functional Description 20 June 19, 2006 IDT82V3255 WAN PLL 3.5.2 FREQUENCY MONITORING Frequency is monitored by comparing the input clock with a reference clock. The reference clock can be derived from the master clock or the output of T0 DPLL, as determined by the FREQ_MON_CLK bit. A frequency hard alarm threshold is set for frequency monitoring. If the FREQ_MON_HARD_EN bit is `1', a frequency hard alarm is raised when the frequency of the input clock with respect to the reference clock is above the threshold; the alarm is cleared when the frequency is below the threshold. The frequency hard alarm threshold can be calculated as follows: Frequency Hard Alarm Threshold (ppm) = (ALL_FREQ_HARD_ THRESHOLD[3:0] + 1) X FREQ_MON_FACTOR[3:0] The input clock with a frequency hard alarm is disqualified for clock selection for T0/T4 DPLL. In addition, if the input clock is 2 kHz, 4 kHz or 8 kHz, its clock edges with respect to the reference clock are monitored. If any edge drifts outside 5%, the input clock is disqualified for clock selection for T0/T4 DPLL. The input clock is qualified if any edge drifts inside 5%. This function is supported only when the IN_NOISE_WINDOW bit is `1'. The frequency of each input clock with respect to the reference clock can be read by doing the following step by step: 1. Select an input clock by setting the IN_FREQ_READ_CH[3:0] bits; 2. Read the value in the IN_FREQ_VALUE[7:0] bits and calculate as follows: Input Clock Frequency (ppm) = IN_FREQ_VALUE[7:0] X FREQ_MON_FACTOR[3:0] If the FREQ_MON_HARD_EN bit is `1', the frequency hard alarm status of the input clock is indicated by the INn_CMOS_FREQ_HARD_ALARM bit (n = 1, 2 or 3) / INn_DIFF_FREQ_HARD_ALARM bit (n = 1 or 2). When the FREQ_MON_HARD_EN bit is `0', no frequency hard alarm is raised even if the input clock is above the frequency hard alarm threshold. Table 5: Related Bit / Register in Chapter 3.5 Bit BUCKET_SIZE_n_DATA[7:0] (3 n 0) UPPER_THRESHOLD_n_DATA[7:0] (3 n 0) LOWER_THRESHOLD_n_DATA[7:0] (3 n 0) DECAY_RATE_n_DATA[1:0] (3 n 0) BUCKET_SEL[1:0] INn_CMOS_NO_ACTIVITY_ALARM (n = 1, 2, or 3) INn_CMOS_FREQ_HARD_ALARM (n = 1, 2 or 3) INn_DIFF_NO_ACTIVITY_ALARM (n = 1 or 2) INn_DIFF_FREQ_HARD_ALARM (n = 1 or 2) FREQ_MON_CLK FREQ_MON_HARD_EN ALL_FREQ_HARD_THRESHOLD[3:0] FREQ_MON_FACTOR[3:0] IN_NOISE_WINDOW IN_FREQ_READ_CH[3:0] IN_FREQ_VALUE[7:0] Note that the value set by the FREQ_MON_FACTOR[3:0] bits depends on the application. Register BUCKET_SIZE_0_CNFG ~ BUCKET_SIZE_3_CNFG UPPER_THRESHOLD_0_CNFG ~ UPPER_THRESHOLD_3_CNFG LOWER_THRESHOLD_0_CNFG ~ LOWER_THRESHOLD_3_CNFG DECAY_RATE_0_CNFG ~ DECAY_RATE_3_CNFG IN1_CMOS_CNFG, IN2_CMOS_CNFG, IN1_DIFF_CNFG, IN2_DIFF_CNFG, IN3_CMOS_CNFG IN1_IN2_CMOS_STS, IN3_CMOS_STS IN1_IN2_DIFF_STS MON_SW_PBO_CNFG ALL_FREQ_MON_THRESHOLD_CNFG FREQ_MON_FACTOR_CNFG PHASE_MON_PBO_CNFG IN_FREQ_READ_CH_CNFG IN_FREQ_READ_STS Address (Hex) 33, 37, 3B, 3F 31, 35, 39, 3D 32, 36, 3A, 3E 34, 38, 3C, 40 16, 17, 19, 1A, 1D 44, 47 45 0B 2F 2E 78 41 42 Functional Description 21 June 19, 2006 IDT82V3255 WAN PLL 3.6 T0 / T4 DPLL INPUT CLOCK SELECTION An input clock is selected for T0 DPLL and for T4 DPLL respectively. For T0 path, the EXT_SW bit and the T0_INPUT_SEL[3:0] bits determine the input clock selection, as shown in Table 6: Table 6: Input Clock Selection for T0 Path Control Bits EXT_SW 1 0 T0_INPUT_SEL[3:0] don't-care other than 0000 0000 Input Clock Selection External Fast selection Forced selection Automatic selection Automatic selection is done based on the results of input clocks quality monitoring and the related registers configuration. The selected input clock is attempted to be locked in T0/T4 DPLL. 3.6.1 EXTERNAL FAST SELECTION (T0 ONLY) The External Fast selection is supported by T0 path only. In External Fast selection, only IN1_CMOS/IN1_DIFF and IN2_CMOS/IN2_DIFF pairs are available for selection. Refer to Figure 5. The results of input clocks quality monitoring (refer to Chapter 3.5 Input Clock Quality Monitoring) do not affect input clock selection. The T0 input clock selection is determined by the FF_SRCSW pin after reset (this pin determines the default value of the EXT_SW bit during reset, refer to Chapter 2 Pin Description), the IN1_CMOS_SEL_PRIORITY[3:0] bits and the IN2_CMOS_SEL_PRIORITY[3:0] bits, as shown in Figure 5 and Table 8: IN1_CMOS_SEL_PRIORITY[3:0] bits FF_SRCSW pin For T4 path, the T4 DPLL may lock to a T0 DPLL output or lock independently from T0 path, as determined by the T4_LOCK_T0 bit. When the T4 DPLL locks to the T0 DPLL output, the T4 selected input clock is a 77.76 MHz or 8 kHz signal from the T0 DPLL 77.76 MHz path (refer to Chapter 3.11.5.1 T0 Path), as determined by the T0_FOR_T4 bit. When the T4 path locks independently from the T0 path, the T4 DPLL input clock selection is determined by the T4_INPUT_SEL[3:0] bits. Refer to Table 7: Table 7: Input Clock Selection for T4 Path Control Bits - T4_INPUT_SEL[3:0] other than 0000 0000 Input Clock Selection Forced selection Automatic selection IN1_CMOS IN1_DIFF attempted to be locked in T0 DPLL IN2_CMOS IN2_DIFF External Fast selection is done between IN1_CMOS/IN1_DIFF and IN2_CMOS/IN2_DIFF pairs. Forced selection is done by setting the related registers. Table 8: External Fast Selection Control Pin & Bits FF_SRCSW (after reset) high low IN1_CMOS_SEL_PRIORITY[3:0] 0000 other than 0000 don't-care IN2_CMOS_SEL_PRIORITY[3:0] bits Figure 5. External Fast Selection IN2_CMOS_SEL_PRIORITY[3:0] don't-care 0000 other than 0000 the Selected Input Clock IN1_DIFF IN1_CMOS IN2_DIFF IN2_CMOS Functional Description 22 June 19, 2006 IDT82V3255 WAN PLL 3.6.2 FORCED SELECTION In Forced selection, the selected input clock is set by the T0_INPUT_SEL[3:0] / T4_INPUT_SEL[3:0] bits. The results of input clocks quality monitoring (refer to Chapter 3.5 Input Clock Quality Monitoring) do not affect the input clock selection. 3.6.3 AUTOMATIC SELECTION In Automatic selection, the input clock selection is determined by its validity and priority. The validity depends on the results of input clock quality monitoring (refer to Chapter 3.5 Input Clock Quality Monitoring). In all the qualified input clocks, the one with the highest priority is selected. The priority is configured by the corresponding INn_CMOS_SEL_PRIORITY[3:0] bits (n = 1, 2 or 3) / the Table 10: Related Bit / Register in Chapter 3.6 Bit EXT_SW T0_INPUT_SEL[3:0] T4_LOCK_T0 T0_FOR_T4 T4_INPUT_SEL[3:0] INn_CMOS_SEL_PRIORITY[3:0] (n = 1, 2 or 3) INn_DIFF_SEL_PRIORITY[3:0] (n = 1 or 2) T4_T0_SEL INn_DIFF_SEL_PRIORITY[3:0] bits (n = 1 or 2). If more than one qualified input clock is available and has the same priority, the input clock with the smallest `n' is selected. See Table 9 for the `n' assigned to the input clock. Table 9: `n' Assigned to the Input Clock Input Clock IN1_CMOS IN1_DIFF IN2_CMOS IN2_DIFF IN3_CMOS `n' Assigned to the Input Clock 1 2 3 4 5 Register MON_SW_PBO_CNFG T0_INPUT_SEL_CNFG T4_INPUT_SEL_CNFG IN1_IN2_CMOS_SEL_PRIORITY_CNFG, IN3_CMOS_SEL_PRIORITY_CNFG IN1_IN2_DIFF_SEL_PRIORITY_CNFG T4_T0_REG_SEL_CNFG Address (Hex) 0B 50 51 27 *, 2A * 28 * 07 Note: * The setting in the 27, 28 and 2A registers is either for T0 path or for T4 path, as determined by the T4_T0_SEL bit. Functional Description 23 June 19, 2006 IDT82V3255 WAN PLL 3.7 SELECTED INPUT CLOCK MONITORING 3.7.1.3 Fine Phase Loss The quality of the selected input clock is always monitored (refer to Chapter 3.5 Input Clock Quality Monitoring) and the DPLL locking status is always monitored. 3.7.1 T0 / T4 DPLL LOCKING DETECTION The following events is always monitored: * Fast Loss; * Coarse Phase Loss; * Fine Phase Loss; * Hard Limit Exceeding. 3.7.1.1 Fast Loss A fast loss is triggered when the selected input clock misses 2 consecutive clock cycles. It is cleared once an active clock edge is detected. For T0 path, the occurrence of the fast loss will result in T0 DPLL unlocked if the FAST_LOS_SW bit is `1'. For T4 path, the occurrence of the fast loss will result in T4 DPLL unlocked regardless of the FAST_LOS_SW bit. 3.7.1.2 Coarse Phase Loss The T0/T4 DPLL compares the selected input clock with the feedback signal. If the phase-compared result exceeds the coarse phase limit, a coarse phase loss is triggered. It is cleared once the phase-compared result is within the coarse phase limit. When the selected input clock is of 2 kHz, 4 kHz or 8 kHz, the coarse phase limit depends on the MULTI_PH_8K_4K_2K_EN bit, the WIDE_EN bit and the PH_LOS_COARSE_LIMT[3:0] bits. Refer to Table 11. When the selected input clock is of other frequencies but 2 kHz, 4 kHz and 8 kHz, the coarse phase limit depends on the WIDE_EN bit and the PH_LOS_COARSE_LIMT[3:0] bits. Refer to Table 12. Table 11: Coarse Phase Limit Programming (the selected input clock of 2 kHz, 4 kHz or 8 kHz) MULTI_PH_8K_4K WIDE_EN _2K_EN 0 1 Coarse Phase Limit The T0/T4 DPLL compares the selected input clock with the feedback signal. If the phase-compared result exceeds the fine phase limit programmed by the PH_LOS_FINE_LIMT[2:0] bits, a fine phase loss is triggered. It is cleared once the phase-compared result is within the fine phase limit. The occurrence of the fine phase loss will result in T0/T4 DPLL unlocked if the FINE_PH_LOS_LIMT_EN bit is `1'. 3.7.1.4 Hard Limit Exceeding Two limits are available for this monitoring. They are DPLL soft limit and DPLL hard limit. When the frequency of the DPLL output with respect to the master clock exceeds the DPLL soft / hard limit, a DPLL soft / hard alarm will be raised; the alarm is cleared once the frequency is within the corresponding limit. The occurrence of the DPLL soft alarm does not affect the T0/T4 DPLL locking status. The DPLL soft alarm is indicated by the corresponding T0_DPLL_SOFT_FREQ_ALARM / T4_DPLL_SOFT_FREQ_ALARM bit. The occurrence of the DPLL hard alarm will result in T0/T4 DPLL unlocked if the FREQ_LIMT_PH_LOS bit is `1'. The DPLL soft limit is set by the DPLL_FREQ_SOFT_LIMT[6:0] bits and can be calculated as follows: DPLL Soft Limit (ppm) = DPLL_FREQ_SOFT_LIMT[6:0] X 0.724 The DPLL hard limit is set by the DPLL_FREQ_HARD_LIMT[15:0] bits and can be calculated as follows: DPLL Hard Limit (ppm) = DPLL_FREQ_HARD_LIMT[15:0] X 0.0014 3.7.2 LOCKING STATUS don't-care 1 UI 0 1 UI 1 set by the PH_LOS_COARSE_LIMT[3:0] bits The DPLL locking status depends on the locking monitoring results. The DPLL is in locked state if none of the following events is triggered during 2 seconds; otherwise, the DPLL is unlocked. * Fast Loss (the FAST_LOS_SW bit is `1'); * Coarse Phase Loss (the COARSE_PH_LOS_LIMT_EN bit is `1'); * Fine Phase Loss (the FINE_PH_LOS_LIMT_EN bit is `1'); * DPLL Hard Alarm (the FREQ_LIMT_PH_LOS bit is `1'). If the FAST_LOS_SW bit, the COARSE_PH_LOS_LIMT_EN bit, the FINE_PH_LOS_LIMT_EN bit or the FREQ_LIMT_PH_LOS bit is `0', the DPLL locking status will not be affected even if the corresponding event is triggered. If all these bits are `0', the DPLL will be in locked state in 2 seconds. The DPLL locking status is indicated by the T0_DPLL_LOCK / T4_DPLL_LOCK bit. The T4_STS 1 bit will be set when the locking status of the T4 DPLL changes (from `lock' to `unlock' or from `unlock' to `lock'). If the T4_STS 2 bit is `1', an interrupt will be generated. Table 12: Coarse Phase Limit Programming (the selected input clock of other than 2 kHz, 4 kHz and 8 kHz) WIDE_EN 0 1 Coarse Phase Limit 1 UI set by the PH_LOS_COARSE_LIMT[3:0] bits The occurrence of the coarse phase loss will result in T0/T4 DPLL unlocked if the COARSE_PH_LOS_LIMT_EN bit is `1'. Functional Description 24 June 19, 2006 IDT82V3255 WAN PLL 3.7.3 PHASE LOCK ALARM (T0 ONLY) A phase lock alarm will be raised when the selected input clock can not be locked in T0 DPLL within a certain period. This period can be calculated as follows: Period (sec.) = TIME_OUT_VALUE[5:0] X MULTI_FACTOR[1:0] The phase lock alarm is indicated by the corresponding INn_CMOS_PH_LOCK_ALARM bit (n = 1, 2 or 3) / INn_DIFF_PH_LOCK_ALARM bit (n = 1 or 2). The phase lock alarm can be cleared by the following two ways, as selected by the PH_ALARM_TIMEOUT bit: Table 13: Related Bit / Register in Chapter 3.7 Bit FAST_LOS_SW PH_LOS_FINE_LIMT[2:0] FINE_PH_LOS_LIMT_EN MULTI_PH_8K_4K_2K_EN WIDE_EN PH_LOS_COARSE_LIMT[3:0] COARSE_PH_LOS_LIMT_EN T0_DPLL_SOFT_FREQ_ALARM T4_DPLL_SOFT_FREQ_ALARM T0_DPLL_LOCK T4_DPLL_LOCK DPLL_FREQ_SOFT_LIMT[6:0] FREQ_LIMT_PH_LOS DPLL_FREQ_HARD_LIMT[15:0] T4_STS 1 T4_STS TIME_OUT_VALUE[5:0] MULTI_FACTOR[1:0] INn_CMOS_PH_LOCK_ALARM (n = 1, 2, or 3) INn_DIFF_PH_LOCK_ALARM (n = 1 or 2) PH_ALARM_TIMEOUT T4_T0_SEL 2 * Be cleared when a `1' is written to the corresponding INn_CMOS_PH_LOCK_ALARM / INn_DIFF_PH_LOCK_ ALARM bit; * Be cleared after the period (= TIME_OUT_VALUE[5:0] X MULTI_FACTOR[1:0] in second) which starts from when the alarm is raised. The selected input clock with a phase lock alarm is disqualified for T0 DPLL locking. Note that no phase lock alarm is raised if the T4 selected input clock can not be locked. Register PHASE_LOSS_FINE_LIMIT_CNFG Address (Hex) 5B * PHASE_LOSS_COARSE_LIMIT_CNFG 5A * OPERATING_STS 52 DPLL_FREQ_SOFT_LIMIT_CNFG DPLL_FREQ_HARD_LIMIT[15:8]_CNFG, DPLL_FREQ_HARD_LIMIT[7:0]_CNFG INTERRUPTS3_STS INTERRUPTS3_ENABLE_CNFG PHASE_ALARM_TIME_OUT_CNFG IN1_IN2_CMOS_STS, IN3_CMOS_STS IN1_IN2_DIFF_STS INPUT_MODE_CNFG T4_T0_REG_SEL_CNFG 65 67, 66 0F 12 08 44, 47 45 09 07 Note: * The setting in the 5A and 5B registers is either for T0 path or for T4 path, as determined by the T4_T0_SEL bit. Functional Description 25 June 19, 2006 IDT82V3255 WAN PLL 3.8 SELECTED INPUT CLOCK SWITCH 3.8.2 SELECTED INPUT CLOCK SWITCH If the input clock is selected by External Fast selection or by Forced selection, it can be switched by setting the related registers (refer to Chapter 3.6.1 External Fast Selection (T0 only) & Chapter 3.6.2 Forced Selection) any time. In this case, whether the input clock is qualified for DPLL locking does not affect the clock switch. If the T4 selected input clock is a T0 DPLL output, it can only be switched by setting the T0_FOR_T4 bit. When the input clock is selected by Automatic selection, the input clock switch depends on its validity and priority. If the current selected input clock is disqualified, a new qualified input clock may be switched to. 3.8.1 INPUT CLOCK VALIDITY For all the input clocks, the validity depends on the results of input clock quality monitoring (refer to Chapter 3.5 Input Clock Quality Monitoring). When all of the following conditions are satisfied, the input clock is valid; otherwise, it is invalid. * No no-activity alarm (the INn_CMOS_NO_ACTIVITY_ALARM / INn_DIFF_NO_ACTIVITY_ALARM bit is `0'); * No frequency hard alarm (the INn_CMOS_FREQ_HARD_ ALARM / INn_DIFF_FREQ_HARD_ALARM bit is `0'); * If the IN_NOISE_WINDOW bit is `1', all the edges of the input clock of 2 kHz, 4 kHz or 8 kHz drift inside 5%; if the IN_NOISE_WINDOW bit is `0', this condition is ignored. The validity qualification of the T0 selected input clock is different from that of the T4 selected input clock. The validity qualification of the T4 selected input clock is the same as the above. The T0 selected input clock is valid when all of the above and the following conditions are satisfied; otherwise, it is invalid. * No phase lock alarm, i.e., the INn_CMOS_PH_LOCK_ALARM / INn_DIFF_PH_LOCK_ALARM bit is `0'; * If the ULTR_FAST_SW bit is `1', the T0 selected input clock misses less than (<) 2 consecutive clock cycles; if the ULTR_FAST_SW bit is `0', this condition is ignored. The validities of all the input clocks are indicated by the INn_CMOS 1 bit (n = 1, 2 or 3) / INn_DIFF 1 bit (n = 1 or 2). When the input clock validity changes (from `valid' to `invalid' or from `invalid' to `valid'), the INn_CMOS 2 / INn_DIFF 2 bit will be set. If the INn_CMOS 3 / INn_DIFF 3 bit is `1', an interrupt will be generated. When the T0 selected input clock has failed, i.e., the validity of the T0 selected input clock changes from `valid' to `invalid', the T0_MAIN_REF_FAILED 1 bit will be set. If the T0_MAIN_REF_FAILED 2 bit is `1', an interrupt will be generated. This interrupt can also be indicated by hardware - the TDO pin, as determined by the LOS_FLAG_TO_TDO bit. When the TDO pin is used to indicate this interrupt, it will be set high when this interrupt is generated and will remain high until this interrupt is cleared. When the device is configured as Automatic input clock selection, T0 input clock switch is different from T4 input clock switch. For T0 path, Revertive and Non-Revertive switches are supported, as selected by the REVERTIVE_MODE bit. For T4 path, only Revertive switch is supported. The difference between Revertive and Non-Revertive switches is that whether the selected input clock is switched when another qualified input clock with a higher priority than the current selected input clock is available for selection. In Non-Revertive switch, input clock switch is minimized. Conditions of the qualified input clocks available for T0 selection are different from that for T4 selection, as shown in Table 14: Table 14: Conditions of Qualified Input Clocks Available for T0 & T4 Selection Conditions of Qualified Input Clocks Available for T0 & T4 Selection * Valid, i.e., the INn_CMOS 1 / INn_DIFF 1 bit is `1'; T0 * Priority enabled, i.e., the corresponding INn_CMOS_SEL _PRIORITY[3:0] / INn_DIFF_SEL_PRIORITY[3:0] bits are not `0000' * Valid (all the validity conditions listed in Chapter 3.8.1 Input Clock Validity are satisfied); T4 * Priority enabled, i.e., the corresponding INn_CMOS_SEL _PRIORITY[3:0] / INn_DIFF_SEL_PRIORITY[3:0] bits are not `0000' The input clock is disqualified if any of the above conditions is not satisfied. In summary, the selected input clock can be switched by: * External Fast selection (supported by T0 path only); * Forced selection; * Revertive switch; * Non-Revertive switch (supported by T0 path only); * T4 DPLL locked to T0 DPLL output (supported by T4 path only). 3.8.2.1 Revertive Switch In Revertive switch, the selected input clock is switched when another qualified input clock with a higher priority than the current selected input clock is available. The selected input clock is switched if any of the following is satisfied: * the selected input clock is disqualified; * another qualified input clock with a higher priority than the selected input clock is available. A qualified input clock with the highest priority is selected by revertive switch. If more than one qualified input clock is available and has the same priority, the input clock with the smallest `n' is selected. See Table 9 for the `n' assigned to each input clock. Functional Description 26 June 19, 2006 IDT82V3255 WAN PLL 3.8.2.2 Non-Revertive Switch (T0 only) In Non-Revertive switch, the T0 selected input clock is not switched when another qualified input clock with a higher priority than the current selected input clock is available. In this case, the selected input clock is switched and a qualified input clock with the highest priority is selected only when the T0 selected input clock is disqualified. If more than one qualified input clock is available and has the same priority, the input clock with the smallest `n' is selected. See Table 9 for the `n' assigned to each input clock. 3.8.3 SELECTED / QUALIFIED INPUT CLOCKS INDICATION The selected input clock is indicated by the CURRENTLY_SELECTED_INPUT[3:0] bits. Note if the T4 selected input clock is a T0 DPLL output, it can not be indicated by these bits. The qualified input clocks with the three highest priorities are indicated by HIGHEST_PRIORITY_VALIDATED[3:0] bits, the SECOND_ PRIORITY_VALIDATED[3:0] bits and the THIRD_PRIORITY _VALIDATED[3:0] bits respectively. If more than one input clock has the same priority, the input clock with the smallest `n' is indicated by the HIGHEST_PRIORITY_VALIDATED[3:0] bits. See Table 9 for the `n' assigned to the input clock. When the device is configured in Automatic selection and Revertive switch is enabled, the input clock indicated by the CURRENTLY_SELECTED_INPUT[3:0] bits is the same as the one indicated by the HIGHEST_PRIORITY_VALIDATED[3:0] bits; otherwise, they are not the same. When all the input clocks for T4 path changes to be unqualified, the INPUT_TO_T4 1 bit will be set. If the INPUT_TO_T4 2 bit is `1', an interrupt will be generated. Table 15: Related Bit / Register in Chapter 3.8 Bit T0_FOR_T4 INn_CMOS 1 (n = 1, 2 or 3) / INn_DIFF 1 (n = 1 or 2) INn_CMOS 2 (n = 1, 2 or 3) / INn_DIFF 2 (n = 1 or 2) INn_CMOS 3 (n = 1, 2 or 3) / INn_DIFF 3 (n = 1 or 2) Register T4_INPUT_SEL_CNFG INPUT_VALID1_STS, INPUT_VALID2_STS INTERRUPTS1_STS, INTERRUPTS2_STS INTERRUPTS1_ENABLE_CNFG, INTERRUPTS2_ENABLE_CNFG IN1_IN2_CMOS_STS, IN3_CMOS_STS Address (Hex) 51 4A, 4B 0D, 0E 10, 11 44, 47 INn_CMOS_NO_ACTIVITY_ALARM (n = 1, 2 or 3) INn_CMOS_FREQ_HARD_ALARM (n = 1, 2 or 3) INn_CMOS_PH_LOCK_ALARM (n = 1, 2 or 3) INn_DIFF_NO_ACTIVITY_ALARM (n = 1 or 2) INn_DIFF_FREQ_HARD_ALARM (n = 1 or 2) INn_DIFF_PH_LOCK_ALARM (n = 1 or 2) IN_NOISE_WINDOW ULTR_FAST_SW LOS_FLAG_TO_TDO T0_MAIN_REF_FAILED 1 T0_MAIN_REF_FAILED 2 INPUT_TO_T4 1 2 IN1_IN2_DIFF_STS PHASE_MON_PBO_CNFG MON_SW_PBO_CNFG INTERRUPTS2_STS INTERRUPTS2_ENABLE_CNFG INTERRUPTS3_STS INTERRUPTS3_ENABLE_CNFG INPUT_MODE_CNFG IN1_IN2_CMOS_SEL_PRIORITY_CNFG, IN3_CMOS_SEL_PRIORITY_CNFG IN1_IN2_DIFF_SEL_PRIORITY_CNFG PRIORITY_TABLE1_STS PRIORITY_TABLE2_STS T4_T0_REG_SEL_CNFG 45 78 0B 0E 11 0F 12 09 27 *, 2A * 28 * 4E * 4F * 07 INPUT_TO_T4 REVERTIVE_MODE INn_CMOS_SEL_PRIORITY[3:0] (n = 1, 2 or 3) INn_DIFF_SEL_PRIORITY[3:0] (n = 1 or 2) CURRENTLY_SELECTED_INPUT[3:0] HIGHEST_PRIORITY_VALIDATED[3:0] SECOND_PRIORITY_VALIDATED[3:0] THIRD_PRIORITY_VALIDATED[3:0] T4_T0_SEL Note: * The setting in the 27, 28, 2A, 4E and 4F registers is either for T0 path or for T4 path, as determined by the T4_T0_SEL bit. Functional Description 27 June 19, 2006 IDT82V3255 WAN PLL 3.9 SELECTED INPUT CLOCK STATUS VS. DPLL OPERATING MODE 3.9.1 T0 SELECTED INPUT CLOCK VS. DPLL OPERATING MODE by the The operating modes supported by T0 DPLL are more complex than the ones supported by T4 DPLL for T0 path is the main one. T0 DPLL supports three primary operating modes: Free-Run, Locked and Holdover, and three secondary, temporary operating modes: Pre-Locked, Pre-Locked2 and Lost-Phase. T4 DPLL supports three operating modes: Free-Run, Locked and Holdover. The operating modes of T0 DPLL and T4 DPLL can be switched automatically or by force, as controlled by the T0_OPERATING_MODE[2:0] / T4_OPERATING_ MODE[2:0] bits respectively. When the operating mode is switched by force, the operating mode switch is under external control and the status of the selected input clock takes no effect to the operating mode selection. The forced operating mode switch is applicable for special cases, such as testing. When the operating mode is switched automatically, the internal state machines for T0 and for T4 automatically determine the operating mode respectively. The T0 DPLL operating mode is controlled T0_OPERATING_MODE[2:0] bits, as shown in Table 16: Table 16: T0 DPLL Operating Mode Control T0_OPERATING_MODE[2:0] 000 001 010 100 101 110 111 T0 DPLL Operating Mode Automatic Forced - Free-Run Forced - Holdover Forced - Locked Forced - Pre-Locked2 Forced - Pre-Locked Forced - Lost-Phase When the operating mode is switched automatically, the operation of the internal state machine is shown in Figure 6. Whether the operating mode is under external control or is switched automatically, the current operating mode is always indicated by the T0_DPLL_OPERATING_MODE[2:0] bits. When the operating mode switches, the T0_OPERATING_MODE 1 bit will be set. If the T0_OPERATING_MODE 2 bit is `1', an interrupt will be generated. Functional Description 28 June 19, 2006 IDT82V3255 WAN PLL 1 Free-Run mode 3 2 4 Pre-Locked mode 5 10 Locked mode 6 Holdover mode 9 8 7 11 15 Pre-Locked2 mode 12 Lost-Phase mode 13 14 Figure 6. T0 Selected Input Clock vs. DPLL Automatic Operating Mode Notes to Figure 6: 1. Reset. 2. An input clock is selected. 3. The T0 selected input clock is disqualified AND No qualified input clock is available. 4. The T0 selected input clock is switched to another one. 5. The T0 selected input clock is locked (the T0_DPLL_LOCK bit is `1'). 6. The T0 selected input clock is disqualified AND No qualified input clock is available. 7. The T0 selected input clock is unlocked (the T0_DPLL_LOCK bit is `0'). 8. The T0 selected input clock is locked again (the T0_DPLL_LOCK bit is `1'). 9. The T0 selected input clock is switched to another one. 10. The T0 selected input clock is locked (the T0_DPLL_LOCK bit is `1'). 11. The T0 selected input clock is disqualified AND No qualified input clock is available. 12. The T0 selected input clock is switched to another one. 13. The T0 selected input clock is disqualified AND No qualified input clock is available. 14. An input clock is selected. 15. The T0 selected input clock is switched to another one. Functional Description 29 June 19, 2006 IDT82V3255 WAN PLL The causes of Item 4, 9, 12, 15 - `the T0 selected input clock is switched to another one' - are: (The T0 selected input clock is disqualified AND Another input clock is switched to) OR (In Revertive switch, a qualified input clock with a higher priority is switched to) OR (The T0 selected input clock is switched to another one by External Fast selection or Forced selection). Refer to Table 14 for details about the input clock qualification for T0 path. 3.9.2 T4 SELECTED INPUT CLOCK VS. DPLL OPERATING MODE by the Notes to Figure 7: 1. Reset. 2. An input clock is selected. 3. (The T4 selected input clock is disqualified) OR (A qualified input clock with a higher priority is switched to) OR (The T4 selected input clock is switched to another one by Forced selection) OR (When T4 DPLL locks to the T0 DPLL output, the T4 selected input clock is switched by setting the T0_FOR_T4 bit). 4. An input clock is selected. 5. No input clock is selected. Refer to Table 14 for details about the input clock qualification for T4 path. Table 18: Related Bit / Register in Chapter 3.9 Bit Register Address (Hex) 53 54 52 0E 11 51 The T4 DPLL operating mode is controlled T4_OPERATING_MODE[2:0] bits, as shown in Table 17: Table 17: T4 DPLL Operating Mode Control T4_OPERATING_MODE[2:0] 000 001 010 100 T4 DPLL Operating Mode Automatic Forced - Free-Run Forced - Holdover Forced - Locked When the operating mode is switched automatically, the operation of the internal state machine is shown in Figure 7: 1 Free-Run mode 2 T0_OPERATING_MODE[2:0] T0_OPERATING_MODE_CNFG T4_OPERATING_MODE[2:0] T4_OPERATING_MODE_CNFG T0_DPLL_OPERATING_MOD E[2:0] OPERATING_STS T0_DPLL_LOCK T0_OPERATING_MODE 1 T0_OPERATING_MODE T0_FOR_T4 2 INTERRUPTS2_STS INTERRUPTS2_ENABLE_CNFG T4_INPUT_SEL_CNFG Locked mode 3 Holdover mode 4 5 Figure 7. T4 Selected Input Clock vs. DPLL Automatic Operating Mode Functional Description 30 June 19, 2006 IDT82V3255 WAN PLL 3.10 T0 / T4 DPLL OPERATING MODE 3.10.1.1 Free-Run Mode The T0/T4 DPLL gives a stable performance in different applications without being affected by operating conditions or silicon process variations. It integrates a PFD (Phase & Frequency Detector), a LPF (Low Pass Filter) and a DCO (Digital Controlled Oscillator), which forms a closed loop. If no input clock is selected, the loop is not closed, and the PFD and LPF do not function. The PFD detects the phase error, including the fast loss, coarse phase loss and fine phase loss (refer to Chapter 3.7.1.1 Fast Loss to Chapter 3.7.1.3 Fine Phase Loss). The averaged phase error of the T0/ T4 DPLL feedback with respect to the selected input clock is indicated by the CURRENT_PH_DATA[15:0] bits. It can be calculated as follows: Averaged Phase Error (ns) = CURRENT_PH_DATA[15:0] X 0.61 In Free-Run mode, the T0 DPLL output refers to the master clock and is not affected by any input clock. The accuracy of the T0 DPLL output is equal to that of the master clock. 3.10.1.2 Pre-Locked Mode In Pre-Locked mode, the T0 DPLL output attempts to track the selected input clock. The Pre-Locked mode is a secondary, temporary mode. 3.10.1.3 Locked Mode In Locked mode, the T0 selected input clock is locked. The phase and frequency offset of the T0 DPLL output track those of the T0 selected input clock. In this mode, if the T0 selected input clock is in fast loss status and the FAST_LOS_SW bit is `1', the T0 DPLL is unlocked (refer to Chapter 3.7.1.1 Fast Loss) and will enter Lost-Phase mode when the operating mode is switched automatically; if the T0 selected input clock is in fast loss status and the FAST_LOS_SW bit is `0', the T0 DPLL locking status is not affected and the T0 DPLL will enter Temp-Holdover mode automatically. 3.10.1.3.1 Temp-Holdover Mode The T0 DPLL will automatically enter Temp-Holdover mode with a selected input clock switch or no qualified input clock available when the operating mode switch is under external control. In Temp-Holdover mode, the T0 DPLL has temporarily lost the selected input clock. The T0 DPLL operation in Temp-Holdover mode and that in Holdover mode are alike (refer to Chapter 3.10.1.5 Holdover Mode) except the frequency offset acquiring methods. See Chapter 3.10.1.5 Holdover Mode for details about the methods. The method is selected by the TEMP_HOLDOVER_MODE[1:0] bits, as shown in Table 19: Table 19: Frequency Offset Control in Temp-Holdover Mode TEMP_HOLDOVER_MODE[1:0] 00 01 10 11 Frequency Offset Acquiring Method the same as that used in Holdover mode Automatic Instantaneous Automatic Fast Averaged Automatic Slow Averaged The LPF filters jitters. Its 3 dB bandwidth and damping factor are programmable. A range of bandwidths and damping factors can be set to meet different application requirements. Generally, the lower the damping factor is, the longer the locking time is and the more the gain is. The DCO controls the DPLL output. The frequency of the DPLL output is always multiplied on the basis of the master clock. The phase and frequency offset of the DPLL output may be locked to those of the selected input clock. The current frequency offset with respect to the master clock is indicated by the CURRENT_DPLL_FREQ[23:0] bits, and can be calculated as follows: Current Frequency Offset (ppm) = CURRENT_DPLL_FREQ[23:0] X 0.000011 3.10.1 T0 DPLL OPERATING MODE The T0 DPLL loop is closed except in Free-Run mode and Holdover mode. For a closed loop, different bandwidths and damping factors can be used depending on DPLL locking stages: starting, acquisition and locked. In the first two seconds when the T0 DPLL attempts to lock to the selected input clock, the starting bandwidth and damping factor are used. They are set by the T0_DPLL_START_BW[4:0] bits and the T0_DPLL_START_DAMPING[2:0] bits respectively. During the acquisition, the acquisition bandwidth and damping factor are used. They are set by the T0_DPLL_ACQ_BW[4:0] bits and the T0_DPLL_ACQ_DAMPING[2:0] bits respectively. When the T0 selected input clock is locked, the locked bandwidth and damping factor are used. They are set by the T0_DPLL_LOCKED_BW[4:0] bits and the T0_DPLL_LOCKED_DAMPING[2:0] bits respectively. The corresponding bandwidth and damping factor are used when the T0 DPLL operates in different DPLL locking stages: starting, acquisition and locked, as controlled by the device automatically. Only the locked bandwidth and damping factor can be used regardless of the T0 DPLL locking stage, as controlled by the AUTO_BW_SEL bit. The device automatically controls the T0 DPLL to exit from TempHoldover mode. 3.10.1.4 Lost-Phase Mode In Lost-Phase mode, the T0 DPLL output attempts to track the selected input clock. The Lost-Phase mode is a secondary, temporary mode. 3.10.1.5 Holdover Mode In Holdover mode, the T0 DPLL resorts to the stored frequency data acquired in Locked mode to control its output. The T0 DPLL output is not Functional Description 31 June 19, 2006 IDT82V3255 WAN PLL phase locked to any input clock. The frequency offset acquiring method is selected by the MAN_HOLDOVER bit, the AUTO_AVG bit and the FAST_AVG bit, as shown in Table 20: Table 20: Frequency Offset Control in Holdover Mode MAN_HOLDOVER 0 1 AUTO_AVG 0 1 don't-care FAST_AVG don't-care 0 1 Frequency Offset Acquiring Method Automatic Instantaneous Automatic Slow Averaged Automatic Fast Averaged Manual 3.10.1.5.1 Automatic Instantaneous By this method, the T0 DPLL freezes at the operating frequency when it enters Holdover mode. The accuracy is 4.4X10-8 ppm. 3.10.1.5.2 Automatic Slow Averaged By this method, an internal IIR (Infinite Impulse Response) filter is employed to get the frequency offset. The IIR filter gives a 3 dB attenuation point corresponding to a period of 110 minutes. The accuracy is 1.1X10-5 ppm. 3.10.1.5.3 Automatic Fast Averaged By this method, an internal IIR (Infinite Impulse Response) filter is employed to get the frequency offset. The IIR filter gives a 3 dB attenuation point corresponding to a period of 8 minutes. The accuracy is 1.1X10-5 ppm. 3.10.1.5.4 Manual By this method, the frequency offset is set by T0_HOLDOVER_FREQ[23:0] bits. The accuracy is 1.1X10-5 ppm. the Table 21: Holdover Frequency Offset Read READ_AVG FAST_AVG 0 1 Offset Value Read from T0_HOLDOVER_FREQ[23:0] don't-care The value is equal to the one written to. The value is acquired by Automatic Slow Averaged 0 method, not equal to the one written to. The value is acquired by Automatic Fast Averaged 1 method, not equal to the one written to. The frequency offset in ppm is calculated as follows: Holdover Frequency Offset (ppm) = T0_HOLDOVER_FREQ[23:0] X 0.000011 3.10.1.6 Pre-Locked2 Mode In Pre-Locked2 mode, the T0 DPLL output attempts to track the selected input clock. The Pre-Locked2 mode is a secondary, temporary mode. 3.10.2 3.10.2.1 T4 DPLL OPERATING MODE Free-Run Mode The T4 path is simpler compared with the T0 path. In Free-Run mode, the T4 DPLL output refers to the master clock and is affected by any input clock. The accuracy of the T4 DPLL output is equal to that of the master clock. 3.10.2.2 Locked Mode In Locked mode, the T4 selected input clock may be locked in the T4 DPLL. When the T4 selected input clock is locked, the phase and frequency offset of the T4 DPLL output track those of the T4 selected input clock; when unlocked, the phase and frequency offset of the T4 DPLL output attempt to track those of the selected input clock. The T4 DPLL loop is closed in Locked mode. Its bandwidth and damping factor are set by the T4_DPLL_LOCKED_BW[1:0] bits and the T4_DPLL_LOCKED_DAMPING[2:0] bits respectively. 3.10.2.3 Holdover Mode In Holdover mode, the T4 DPLL resorts to the stored frequency data acquired in Locked mode to control its output. The T4 DPLL output is not The frequency offset of the T0 DPLL output is indicated by the CURRENT_DPLL_FREQ[23:0] bits. The device provides a reference for the value to be written to the T0_HOLDOVER_FREQ[23:0] bits. The value to be written can refer to the value read from the CURRENT_DPLL_FREQ[23:0] bits or the T0_HOLDOVER_FREQ[23:0] bits (refer to Chapter 3.10.1.5.5 Holdover Frequency Offset Read); or then be processed by external software filtering. 3.10.1.5.5 Holdover Frequency Offset Read The offset value, which is acquired by Automatic Slow Averaged, Automatic Fast Averaged and is set by related register bits, can be read from the T0_HOLDOVER_FREQ[23:0] bits by setting the READ_AVG bit and the FAST_AVG bit, as shown in Table 21. Functional Description 32 June 19, 2006 IDT82V3255 WAN PLL phase locked to any input clock. The T4 DPLL freezes at the operating frequency when it enters Holdover mode. The accuracy is 4.4X10-8 ppm. Table 22: Related Bit / Register in Chapter 3.10 Bit CURRENT_PH_DATA[15:0] CURRENT_DPLL_FREQ[23:0] T0_DPLL_START_BW[4:0] T0_DPLL_START_DAMPING[2:0] T0_DPLL_ACQ_BW[4:0] T0_DPLL_ACQ_DAMPING[2:0] T0_DPLL_LOCKED_BW[4:0] T0_DPLL_LOCKED_DAMPING[2:0] AUTO_BW_SEL FAST_LOS_SW TEMP_HOLDOVER_MODE[1:0] MAN_HOLDOVER AUTO_AVG FAST_AVG READ_AVG T0_HOLDOVER_FREQ[23:0] T4_DPLL_LOCKED_BW[1:0] T4_DPLL_LOCKED_DAMPING[2:0] T4_T0_SEL Register CURRENT_DPLL_PHASE[15:8]_STS, CURRENT_DPLL_PHASE[7:0]_STS CURRENT_DPLL_FREQ[23:16]_STS, CURRENT_DPLL_FREQ[15:8]_STS, CURRENT_DPLL_FREQ[7:0]_STS T0_DPLL_START_BW_DAMPING_CNFG T0_DPLL_ACQ_BW_DAMPING_CNFG T0_DPLL_LOCKED_BW_DAMPING_CNFG T0_BW_OVERSHOOT_CNFG PHASE_LOSS_FINE_LIMIT_CNFG Address (Hex) 69 *, 68 * 64 *, 63 *, 62 * 56 57 58 59 5B * T0_HOLDOVER_MODE_CNFG 5C T0_HOLDOVER_FREQ[23:16]_CNFG, T0_HOLDOVER_FREQ[15:8]_CNFG, T0_HOLDOVER_FREQ[7:0]_CNFG T4_DPLL_LOCKED_BW_DAMPING_CNFG T4_T0_REG_SEL_CNFG 5F, 5E, 5D 61 07 Note: * The setting in the 5B, 62 ~ 64, 68 and 69 registers is either for T0 path or for T4 path, as determined by the T4_T0_SEL bit. Functional Description 33 June 19, 2006 IDT82V3255 WAN PLL 3.11 T0 / T4 DPLL OUTPUT The DPLL output is locked to the selected input clock. According to the phase-compared result of the feedback and the selected input clock, and the DPLL output frequency offset, the PFD output is limited and the DPLL output is frequency offset limited. 3.11.1 PFD OUTPUT LIMIT The PFD output is limited to be within 1 UI or within the coarse phase limit (refer to Chapter 3.7.1.2 Coarse Phase Loss), as determined by the MULTI_PH_APP bit. 3.11.2 FREQUENCY OFFSET LIMIT The DPLL output is limited to be within the DPLL hard limit (refer to Chapter 3.7.1.4 Hard Limit Exceeding). For T0 DPLL, the integral path value can be frozen when the DPLL hard limit is reached. This function, enabled by the T0_LIMT bit, will minimize the subsequent overshoot when T0 DPLL is pulling in. 3.11.3 PBO (T0 ONLY) The PBO function is only supported by the T0 path. When a PBO event is triggered, the phase offset of the selected input clock with respect to the T0 DPLL output is measured. The device then automatically accounts for the measured phase offset and compensates an appropriate phase offset into the DPLL output so that the phase transients on the T0 DPLL output are minimized. A PBO event is triggered if any one of the following conditions occurs: * T0 selected input clock switches (the PBO_EN bit is `1'); * T0 DPLL exits from Holdover mode or Free-Run mode (the PBO_EN bit is `1'); * Phase-time changes on the T0 selected input clock are greater than a programmable limit over an interval of less than 0.1 seconds (the PH_MON_PBO_EN bit is `1'). For the first two conditions, the phase transients on the T0 DPLL output are minimized to be no more than 0.61 ns with PBO. The PBO can also be frozen at the current phase offset by setting the PBO_FREZ bit. When the PBO is frozen, the device will ignore any further PBO events triggered by the above two conditions, and maintain the current phase offset. When the PBO is disabled, there may be a phase shift on the T0 DPLL output and the T0 DPLL output tracks back to 0 degree phase offset with respect to the T0 selected input clock. The last condition is specially for stratum 2 and 3E clocks. The PBO requirement specified in the Telcordia GR-1244-CORE is: `Input phasetime changes of 3.5 s or greater over an interval of less than 0.1 seconds or less shall be built-out by stratum 2 and 3E clocks to reduce the resulting clock phase-time change to less than 50 ns. Phase-time changes of 1.0 s or less over an interval of 0.1 seconds shall not be built-out.' Based on this requirement, phase-time changes of more than 1.0 s but less than 3.5 s that occur over an interval of less than 0.1 seconds may or may not be built-out. An integrated Phase Transient Monitor can be enabled by the PH_MON_EN bit to monitor the phase-time changes on the T0 selected input clock. When the phase-time changes are greater than a limit over an interval of less than 0.1 seconds, a PBO event is triggered and the phase transients on the DPLL output are absorbed. The limit is programmed by the PH_TR_MON_LIMT[3:0] bits, and can be calculated as follows: Limit (ns) = (PH_TR_MON_LIMT[3:0] + 7) X 156 The phase offset induced by PBO will never result in a coarse or fine phase loss. 3.11.4 PHASE OFFSET SELECTION (T0 ONLY) The phase offset of the T0 selected input clock with respect to the T0 DPLL output can be adjusted. The PH_OFFSET_EN bit determines whether the input-to-output phase offset is enabled. If enabled, the input-to-output phase offset can be adjusted by setting the PH_OFFSET[9:0] bits. The input-to-output phase offset can be calculated as follows: Phase Offset (ns) = PH_OFFSET[9:0] X 0.61 3.11.5 FOUR PATHS OF T0 / T4 DPLL OUTPUTS The T0 DPLL output and the T4 DPLL output are phase aligned with the T0 selected input clock and the T4 selected input clock respectively every 125 s period. Each DPLL has four output paths. 3.11.5.1 T0 Path The four paths for T0 DPLL output are as follows: * 77.76 MHz path - outputs a 77.76 MHz clock; * 16E1/16T1 path - outputs a 16E1 or 16T1 clock, as selected by the IN_SONET_SDH bit; * GSM/OBSAI/16E1/16T1 path - outputs a GSM, OBSAI, 16E1 or 16T1 clock, as selected by the T0_GSM_OBSAI_16E1_16T1_ SEL[1:0] bits; * 12E1/24T1/E3/T3 path - outputs a 12E1, 24T1, E3 or T3 clock, as selected by the T0_12E1_24T1_E3_T3_SEL[1:0] bits. T0 selected input clock is compared with a T0 DPLL output for DPLL locking. The output can only be derived from the 77.76 MHz path or the 16E1/16T1 path. The output path is automatically selected and the output is automatically divided to get the same frequency as the T0 selected input clock. The T0 DPLL 77.76 MHz output or an 8 kHz signal derived from it can be provided for the T4 DPLL input clock selection (refer to Chapter 3.6 T0 / T4 DPLL Input Clock Selection). T0 DPLL outputs are provided for T0/T4 APLL or device output process. Functional Description 34 June 19, 2006 IDT82V3255 WAN PLL 3.11.5.2 T4 Path The four paths for T4 DPLL output are as follows: * 77.76 MHz path - outputs a 77.76 MHz clock; * 16E1/16T1 path - outputs a 16E1 or 16T1 clock, as selected by the IN_SONET_SDH bit; * GSM/GPS/16E1/16T1 path - outputs a GSM, GPS, 16E1 or 16T1 clock, as selected by the T4_GSM_GPS_16E1_16T1_ SEL[1:0] bits; * 12E1/24T1/E3/T3 path - outputs a 12E1, 24T1, E3 or T3 clock, as selected by the T4_12E1_24T1_E3_T3_SEL[1:0] bits. T4 selected input clock is compared with a T4 DPLL output for DPLL locking. The output can be derived from the 77.76 MHz path or the Table 23: Related Bit / Register in Chapter 3.11 Bit MULTI_PH_APP T0_LIMT PBO_EN PBO_FREZ PH_MON_PBO_EN PH_MON_EN PH_TR_MON_LIMT[3:0] PH_OFFSET_EN PH_OFFSET[9:0] IN_SONET_SDH T0_GSM_OBSAI_16E1_16T1_SEL[1:0] T0_12E1_24T1_E3_T3_SEL[1:0] T4_GSM_GPS_16E1_16T1_SEL[1:0] T4_12E1_24T1_E3_T3_SEL[1:0] T4_TEST_T0_PH T4_T0_SEL 16E1/16T1 path. In this case, the output path is automatically selected and the output is automatically divided to get the same frequency as the T4 selected input clock. In addition, T4 selected input clock is compared with the T0 selected input clock to get the phase difference between T0 and T4 selected input clocks, as determined by the T4_TEST_T0_PH bit. T4 DPLL outputs are provided for T0/T4 APLL or device output process. Register PHASE_LOSS_COARSE_LIMIT_CNFG T0_BW_OVERSHOOT_CNFG MON_SW_PBO_CNFG PHASE_MON_PBO_CNFG PHASE_OFFSET[9:8]_CNFG PHASE_OFFSET[9:8]_CNFG, PHASE_OFFSET[7:0]_CNFG INPUT_MODE_CNFG T0_DPLL_APLL_PATH_CNFG T4_DPLL_APLL_PATH_CNFG T4_INPUT_SEL_CNFG T4_T0_REG_SEL_CNFG Address (Hex) 5A * 59 0B 78 7B 7B, 7A 09 55 60 51 07 Note: * The setting in the 5A register is either for T0 path or for T4 path, as determined by the T4_T0_SEL bit. Functional Description 35 June 19, 2006 IDT82V3255 WAN PLL 3.12 T0 / T4 APLL 3.13 OUTPUT CLOCKS & FRAME SYNC SIGNALS A T0 APLL and a T4 APLL are provided for a better jitter and wander performance of the device output clocks. The bandwidths of the T0/T4 APLL are set by the T0_APLL_BW[1:0] / T4_APLL_BW[1:0] bits respectively. The lower the bandwidth is, the better the jitter and wander performance of the T0/T4 APLL output are. The input of the T0/T4 APLL can be derived from one of the T0 and T4 DPLL outputs, as selected by the T0_APLL_PATH[3:0] / T4_APLL_PATH[3:0] bits respectively. Both the APLL and DPLL outputs are provided for selection for the device output. Table 24: Related Bit / Register in Chapter 3.12 Bit T0_APLL_BW[1:0] T4_APLL_BW[1:0] T0_APLL_PATH[3:0] T4_APLL_PATH[3:0] Register T0_T4_APLL_BW_CNFG T0_DPLL_APLL_PATH_CNFG T4_DPLL_APLL_PATH_CNFG Address (Hex) 6A 55 60 The device supports 2 output clocks and 2 frame sync output signals altogether. 3.13.1 OUTPUT CLOCKS The device provides 2 output clocks. OUT1 outputs a PECL or LVDS signal, as selected by the OUT1_PECL_LVDS bit. OUT2 outputs a CMOS signal. The outputs on OUT1 and OUT2 are variable, depending on the signals derived from the T0/T4 DPLL and T0/T4 APLL outputs, and the corresponding OUTn_PATH_SEL[3:0] bits (n = 1 or 2). The derived signal can be from the T0/T4 DPLL and T0/T4 APLL outputs, as selected by the corresponding OUTn_PATH_SEL[3:0] bits (n = 1 or 2). If the signal is derived from one of the T0/T4 DPLL outputs, please refer to Table 25 for the output frequency. If the signal is derived from the T0/T4 APLL output, please refer to Table 26 for the output frequency. The outputs on OUT1 and OUT2 can be inverted, as determined by the corresponding OUTn_INV bit (n = 1 or 2). Both the output clocks derived from T0/T4 selected input clock are aligned with the T0/T4 selected input clock respectively every 125 s period. Table 25: Outputs on OUT1 & OUT2 if Derived from T0/T4 DPLL Outputs OUTn_DIVIDER[3:0] (Output Divider) 1 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 outputs on OUT1 & OUT2 if derived from T0/T4 DPLL outputs 2 77.76 MHz 12E1 16E1 24T1 16T1 E3 T3 GSM (26 MHz) OBSAI (30.72 MHz) GPS (40 MHz) Output is disabled (output low). 12E1 6E1 3E1 2E1 E1 E1 T1 64 kHz 8 kHz 2 kHz 400 Hz 1Hz Output is disabled (output high). 16E1 8E1 4E1 2E1 24T1 12T1 6T1 4T1 3T1 2T1 16T1 8T1 4T1 2T1 T1 E3 T3 13 MHz 15.36 MHz 20 10 5 Note: 1. n = 1 or 2. Each output is assigned a frequency divider. 2. E1 = 2.048 MHz, T1 = 1.544 MHz, E3 = 34.368 MHz, T3 = 44.736 MHz. The blank cell means the configuration is reserved. Functional Description 36 June 19, 2006 IDT82V3255 WAN PLL Table 26: Outputs on OUT1 & OUT2 if Derived from T0/T4 APLL OUTn_DIVIDER[3:0] (Output Divider) 1 77.76 MHz X 4 12E1 X 4 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 6.48 MHz E1 E1 T1 Output is disabled (output high). 622.08 MHz 3 outputs on OUT1 & OUT2 if derived from T0/T4 APLL output 2 16E1 X 4 24T1 X 4 16T1 X 4 E3 T3 GSM OBSAI (26 MHz X 2) (30.72 MHz X 10) GPS (40 MHz) Output is disabled (output low). 311.04 MHz 3 155.52 MHz 77.76 MHz 51.84 MHz 38.88 MHz 25.92 MHz 19.44 MHz 48E1 24E1 12E1 8E1 6E1 4E1 3E1 2E1 2E1 64E1 32E1 16E1 8E1 4E1 96T1 48T1 24T1 16T1 12T1 8T1 6T1 4T1 3T1 2T1 T1 2T1 64T1 32T1 16T1 8T1 4T1 61.44 MHz 4 30.72 MHz 4 15.36 MHz 4 7.68 MHz 4 3.84 MHz 4 E3 T3 52 MHz 26 MHz 13 MHz 153.6 MHz 76.8 MHz 38.4 MHz 20 MHz 10 MHz 5 MHz Note: 1. n = 1 or 2. Each output is assigned a frequency divider. 2. In the APLL, the selected T0/T4 DPLL output may be multiplied. E1 = 2.048 MHz, T1 = 1.544 MHz, E3 = 34.368 MHz, T3 = 44.736 MHz. The blank cell means the configuration is reserved. 3. The 622.08 MHz and 311.04 MHz differential signals are only output on OUT1. 4. The 61.44 MHz, 30.72 MHz, 15.36 MHz, 7.68 MHz and 3.84 MHz outputs are only derived from T0 APLL. Functional Description 37 June 19, 2006 IDT82V3255 WAN PLL 3.13.2 FRAME SYNC OUTPUT SIGNALS An 8 kHz and a 2 kHz frame sync signals are output on the FRSYNC_8K and MFRSYNC_2K pins if enabled by the 8K_EN and 2K_EN bits respectively. They are CMOS outputs. The two frame sync signals are derived from the T0 APLL output and are aligned with the output clock. They can be synchronized to one of the three frame sync input signals. One of the three frame sync input signals is selected, as determined by the SYNC_BYPASS bit and the T0 selected input clock, as shown in Table 27: Table 27: Frame Sync Input Signal Selection SYNC_BYPASS T0 Selected Input Clock 0 1 don't-care IN1_CMOS or IN1_DIFF IN2_CMOS or IN2_DIFF IN3_CMOS none Selected Frame Sync Input Signal EX_SYNC1 EX_SYNC1 EX_SYNC2 EX_SYNC3 none limit, whether the selected frame sync input signal is enabled to synchronize the frame sync output signal is determined by the SYNC_BYPASS bit, the AUTO_EXT_SYNC_EN bit and the EXT_SYNC_EN bit. Refer to Table 28 for details. When the selected frame sync input signal is enabled to synchronize the frame sync output signal, it should be adjusted to align itself with the T0 selected input clock. Nominally, the falling edge of the selected frame sync input signal is aligned with the rising edge of the T0 selected input clock. The selected frame sync input signal may be 0.5 UI early/late or 1 UI late due to the circuit and board wiring delays. Setting the sampling of the selected frame sync input signal by the SYNC_PHn[1:0] bits (n = 1, 2 or 3 corresponding to EX_SYNC1, EX_SYNC2 or EX_SYCN3 respectively) will compensate this early/late. Refer to Figure 8 to Figure 11. The EX_SYNC_ALARM_MON bit indicates whether the selected frame sync input signal is in external sync alarm status. The external sync alarm is indicated by the EX_SYNC_ALARM 1 bit. If the EX_SYNC_ALARM 2 bit is `1', the occurrence of the external sync alarm will trigger an interrupt. The 8 kHz and the 2 kHz frame sync output signals can be inverted by setting the 8K_INV and 2K_INV bits respectively. The frame sync outputs can be 50:50 duty cycle or pulsed, as determined by the 8K_PUL and 2K_PUL bits respectively. When they are pulsed, the pulse width is defined by the period of OUT2; and they are pulsed on the position of the falling or rising edge of the standard 50:50 duty cycle, as selected by the 2K_8K_PUL_POSITION bit. If the selected frame sync input signal with respect to the T0 selected input clock is above a limit set by the SYNC_MON_LIMT[2:0] bits, an external sync alarm will be raised and the selected frame sync input signal is disabled to synchronize the frame sync output signals. The external sync alarm is cleared once the selected frame sync input signal with respect to the T0 selected input clock is within the limit. If it is within the Table 28: Synchronization Control SYNC_BYPASS 0 1 AUTO_EXT_SYNC_EN don't-care 0 1 don't-care EXT_SYNC_EN 0 1 1 Synchronization Disabled Enabled Disabled Enabled T0 selected input clock Selected frame sync input signal Frame sync output signals Output clocks T0 selected input clock Selected frame sync input signal Frame sync output signals Output clocks Figure 8. On Target Frame Sync Input Signal Timing Figure 9. 0.5 UI Early Frame Sync Input Signal Timing Functional Description 38 June 19, 2006 IDT82V3255 WAN PLL T0 selected input clock Selected frame sync input signal Frame sync output signals Output clocks T0 selected input clock Selected frame sync input signal Frame sync output signals Output clocks Figure 10. 0.5 UI Late Frame Sync Input Signal Timing Table 29: Related Bit / Register in Chapter 3.13 Bit OUT1_PECL_LVDS OUTn_PATH_SEL[3:0] (n = 1 or 2) OUTn_DIVIDER[3:0] (n = 1 or 2) IN_SONET_SDH AUTO_EXT_SYNC_EN EXT_SYNC_EN OUTn_INV (n = 1 or 2) 8K_EN 2K_EN 8K_INV 2K_INV 8K_PUL 2K_PUL 2K_8K_PUL_POSITION SYNC_BYPASS SYNC_MON_LIMT[2:0] Figure 11. 1 UI Late Frame Sync Input Signal Timing Register DIFFERENTIAL_IN_OUT_OSCI_CNFG OUT1_FREQ_CNFG, OUT2_FREQ_CNFG INPUT_MODE_CNFG OUT1_INV_CNFG, OUT2_INV_CNFG Address (Hex) 0A 71, 6D 09 73, 72 FR_MFR_SYNC_CNFG 74 SYNC_MONITOR_CNFG SYNC_PHASE_CNFG OPERATING_STS INTERRUPTS3_STS INTERRUPTS3_ENABLE_CNFG 7C 7D 52 0F 12 SYNC_PHn[1:0] (n = 1, 2 or 3) EX_SYNC_ALARM_MON EX_SYNC_ALARM 1 EX_SYNC_ALARM 2 Functional Description 39 June 19, 2006 IDT82V3255 WAN PLL 3.14 INTERRUPT SUMMARY 3.15 T0 AND T4 SUMMARY The interrupt sources of the device are as follows: * T4 DPLL locking status change * Input clocks for T0 path validity change * T0 selected input clock fail * Input clocks for T4 path change to be no qualified input clock available * T0 DPLL operating mode switch * External sync alarm All of the above interrupt events are indicated by the corresponding interrupt status bit. If the corresponding interrupt enable bit is set, any of the interrupts can be reported by the INT_REQ pin. The output characteristics on the INT_REQ pin are determined by the HZ_EN bit and the INT_POL bit. Interrupt events are cleared by writing a `1' to the corresponding interrupt status bit. The INT_REQ pin will be inactive only when all the pending enabled interrupts are cleared. In addition, the interrupt of T0 selected input clock fail can be reported by the TDO pin, as determined by the LOS_FLAG_TO_TDO bit. Table 30: Related Bit / Register in Chapter 3.14 Bit HZ_EN INT_POL LOS_FLAG_TO_TDO Register INTERRUPT_CNFG MON_SW_PBO_CNFG Address (Hex) 0C 0B The main features supported by the T0 path are as follows: * Phase lock alarm; * Forced or Automatic input clock selection/switch; * 3 primary and 3 secondary, temporary DPLL operating modes, switched automatically or under external control; * Automatic switch between starting, acquisition and locked bandwidths/damping factors; * Programmable DPLL bandwidths from 0.1 Hz to 560 Hz in 11 steps; * Programmable damping factors: 1.2, 2.5, 5, 10 and 20; * Fast loss, coarse phase loss, fine phase loss and hard limit exceeding monitoring; * Output phase and frequency offset limited; * Automatic Instantaneous, Automatic Slow Averaged, Automatic Fast Averaged or Manual holdover frequency offset acquiring; * PBO to minimize output phase transients; * Programmable output phase offset; * Low jitter multiple clock outputs with programmable polarity; * Low jitter 2 kHz and 8 kHz frame sync signal outputs with programmable pulse width and polarity; The main features supported by the T4 path are as follows: * Forced or Automatic input clock selection/switch; * Locking to T0 DPLL output; * 3 DPLL operating modes, switched automatically or under external control; * Programmable DPLL bandwidth: 18 Hz, 35 Hz, 70 Hz and 560 Hz; * Programmable damping factor: 1.2, 2.5, 5, 10 and 20; * Fast loss, coarse phase loss, fine phase loss and hard limit exceeding monitoring; * Output phase and frequency offset limited; * Automatic Instantaneous holdover frequency offset; * Low jitter multiple clock outputs with programmable polarity. Functional Description 40 June 19, 2006 IDT82V3255 WAN PLL 3.16 POWER SUPPLY FILTERING TECHNIQUES 3. 3V SLF7028T-100M1R1 0.1 F 10 F 0.1 F 0.1 F VDDA 0.1 F IDT 82 V3255 4, 14, 57 1, 3, 15, 58 7, 10, 11, 31, 40, 53 VDD _DIFF 22 21 AGND DGND GND_DIFF 3.3V SLF7028T-100M1R1 10 F 0.1 F 0.1 F 0.1 F 0.1 F 0.1 F 0.1 F 0.1 F 0 .1 F 0.1 F VDDD 0.1 F 8, 9, 12, 32, 36, 38, 39, 45, 46 , 54 Figure 12. IDT82V3255 Power Decoupling Scheme To achieve optimum jitter performance, power supply filtering is required to minimize supply noise modulation of the output clocks. The common sources of power supply noise are switch power supplies and the high switching noise from the outputs to the internal PLL. The 82V3255 provides separate VDDA power pins for the internal analog PLL, VDD_DIFF for the differential output driver circuit and VDDD pins for the core logic as well as I/O driver circuits. To minimize switching power supply noise generated by the switching regulator, the power supply output should be filtering with sufficient bulk capacity to minimize ripple and 0.1 uF (0402 case size, ceramic) caps to filter out the switching transients. For the 82V3255, the decoupling for VDDA, VDD_DIFF and VDDD are handled individually. VDDD, VDD_DIFF and VDDA should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. Figure 12 illustrated how bypass capacitor and ferrite bead should be connected to power pins. The analog power supply VDDA and VDD_DIFF should have low impedance. This can be achieved by using one 10 uF (1210 case size, ceramic) and at least four 0.1 uF (0402 case size, ceramic) capacitors in parallel. The 0.1 uF (0402 case size, ceramic) capacitors must be placed right next to the VDDA and VDD_DIFF pins as close as possible. Note that the 10 uF capacitor must be of 1210 case size, and it must be ceramic for lowest ESR (Effective Series Resistance) possible. The 0.1 uF should be of case size 0402, this offers the lowest ESL (Effective Series Inductance) to achieve low impedance towards the high speed range. For VDDD, at least ten 0.1 uF (0402 case size, ceramic) and one 10 uF (1210 case size, ceramic) capacitors are recommended. The 0.1 uF capacitors should be placed as close to the VDDD pins as possible. Please refer to evaluation board schematic for details. Functional Description 41 June 19, 2006 IDT82V3255 WAN PLL 3.17 LINE CARD APPLICATION Master Clock Board Clock Sync Slave Clock Board Clock Sync Clock Sync IDT82V3255 Sync OC-N Clock SDH/SONET System Chip e.g. Transciever TSE ...... Optical signal 155 M, 622 M, 2.5 G, or 10 Gbit/s Standby Clock Board Backplane OC-n Line Card Board Figure 13. Line Card Application Functional Description 42 June 19, 2006 IDT82V3255 WAN PLL 4 MICROPROCESSOR INTERFACE ing edge of SCLK. When CLKE is asserted high, data on SDO will be clocked out on the falling edge of SCLK. In a write operation, data on SDI will be clocked in on the rising edge of SCLK. The microprocessor interface provides access to read and write the registers in the device. The microprocessor interface supports Serial mode only. In a read operation, the active edge of SCLK is selected by CLKE. When CLKE is asserted low, data on SDO will be clocked out on the ris- CS tsu2 SCLK tsu1 SDI th1 tpw1 A0 A1 A2 A3 A4 A5 A6 tpw2 th2 R/W td1 SDO High-Z D0 D1 D2 D3 D4 D5 D6 td2 D7 Figure 14. Serial Read Timing Diagram (CLKE Asserted Low) CS th2 SCLK SDI R/W A0 A1 A2 A3 A4 A5 A6 td1 High-Z td2 D0 D1 D2 D3 D4 D5 D6 D7 SDO Figure 15. Serial Read Timing Diagram (CLKE Asserted High) Microprocessor Interface 43 June 19, 2006 IDT82V3255 WAN PLL Table 31: Read Timing Characteristics in Serial Mode Symbol T tin tout tsu1 tsu2 td1 td2 tpw1 tpw2 th1 th2 tTI Parameter One cycle time of the master clock Delay of input pad Delay of output pad Valid SDI to valid SCLK setup time Valid CS to valid SCLK setup time Valid SCLK to valid data delay time CS rising edge to SDO high impedance delay time SCLK pulse width low SCLK pulse width high Valid SDI after valid SCLK hold time Valid CS after valid SCLK hold time (CLKE = 0/1) Time between consecutive Read-Read or Read-Write accesses (CS rising edge to CS falling edge) 3.5T + 5 3.5T + 5 6 5 10 4 14 10 10 Min Typ 12.86 5 5 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns CS tsu2 SCLK tsu1 SDI SDO R/W A0 A1 A2 tpw2 th2 th1 tpw1 A3 A4 A5 A6 D0 D1 D2 D3 D4 D5 D6 D7 High-Z Figure 16. Serial Write Timing Diagram Table 32: Write Timing Characteristics in Serial Mode Symbol T tin tout tsu1 tsu2 tpw1 tpw2 th1 th2 tTI Parameter One cycle time of the master clock Delay of input pad Delay of output pad Valid SDI to valid SCLK setup time Valid CS to valid SCLK setup time SCLK pulse width low SCLK pulse width high Valid SDI after valid SCLK hold time Valid CS after valid SCLK hold time Time between consecutive Write-Write or Write-Read accesses (CS rising edge to CS falling edge) 4 14 3.5T 3.5T 6 5 10 Min Typ 12.86 5 5 Max Unit ns ns ns ns ns ns ns ns ns ns Microprocessor Interface 44 June 19, 2006 IDT82V3255 WAN PLL 5 JTAG This device is compliant with the IEEE 1149.1 Boundary Scan standard except the following: * The output boundary scan cells do not capture data from the core and the device does not support EXTEST instruction; * The TRST pin is set low by default and JTAG is disabled in order to be consistent with other manufacturers. The JTAG interface timing diagram is shown in Figure 17. tTCK TCK tS TMS TDI tH tD TDO Figure 17. JTAG Interface Timing Diagram Table 33: JTAG Timing Characteristics Symbol tTCK tS tH tD Parameter TCK period TMS / TDI to TCK setup time TCK to TMS / TDI Hold Time TCK to TDO delay time Min 100 25 25 50 Typ Max Unit ns ns ns ns JTAG 45 June 19, 2006 IDT82V3255 WAN PLL 6 PROGRAMMING INFORMATION The access of the Multi-word Registers is different from that of the Single-word Registers. Take the registers (04H, 05H and 06H) for an example, the write operation for the Multi-word Registers follows a fixed sequence. The register (04H) is configured first and the register (06H) is configured last. The three registers are configured continuously and should not be interrupted by any operation. The crystal calibration configuration will take effect after all the three registers are configured. During read operation, the register (04H) is read first and the register (06H) is read last. The crystal calibration reading should be continuous and not be interrupted by any operation. Certain bit locations within the device register map are designated as Reserved. To ensure proper and predictable operation, bits designated as Reserved should not be written by the users. In addition, their value should be masked out from any testing or error detection methods that are implemented. After reset, all the registers are set to their default values. The registers are read or written via the microprocessor interface. Before any write operation, the value in register PROTECTION_CNFG is recommended to be confirmed to make sure whether the write operation is enabled. The device provides 3 register protection modes: * Protected mode: no other registers can be written except register PROTECTION_CNFG itself; * Fully Unprotected mode: all the writable registers can be written; * Single Unprotected mode: one more register can be written besides register PROTECTION_CNFG. After write operation (not including writing a `1' to clear a bit to `0'), the device automatically switches to Protected mode. Writing `0' to the registers will take no effect if the registers are cleared by writing `1'. T0 and T4 paths share some registers, whose addresses are 27H, 28H, 2AH, 4EH, 4FH, 5AH, 5BH, 62H ~ 64H, 68H and 69H. The names of shared registers are marked with a *. Before register read/write operation, register T4_T0_REG_SEL_CNFG is recommended to be confirmed to make sure whether the register operation is available for T0 or T4 path. Table 34: Register List and Map Address (Hex) 00 01 04 Register Name Bit 7 Bit 6 Bit 5 6.1 REGISTER MAP Table 34 is the map of all the registers, sorted in an ascending order of their addresses. Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reference Page P 51 P 51 P 52 Global Control Registers ID[7:0] - Device ID 1 ID[15:8] - Device ID 2 NOMINAL_FREQ[7:0]_CNFG - Crystal Oscillator Frequency Offset Calibration Configuration 1 NOMINAL_FREQ[15:8]_CNFG - Crystal Oscillator Frequency Offset Calibration Configuration 2 NOMINAL_FREQ[23:16]_CNFG Crystal Oscillator Frequency Offset Calibration Configuration 3 T4_T0_REG_SEL_CNFG - T0 / T4 Registers Selection Configuration PHASE_ALARM_TIME_OUT_CNFG Phase Lock Alarm Time-Out Configuration ID[7:0] ID[15:8] NOMINAL_FREQ_VALUE[7:0] 05 NOMINAL_FREQ_VALUE[15:8] P 52 06 07 08 NOMINAL_FREQ_VALUE[23:16] T4_T0_SE L - P 52 P 53 P 53 REVERTIV E_MODE - MULTI_FACTOR[1:0] TIME_OUT_VALUE[5:0] IN_SONET _SDH 09 0A AUTO_EX PH_ALAR INPUT_MODE_CNFG - Input Mode EXT_SYN T_SYNC_ M_TIMEO Configuration C_EN EN UT DIFFERENTIAL_IN_OUT_OSCI_CNF G - Differential Input / Output Port & Master Clock Configuration SYNC_FREQ[1:0] - P 54 - - OSC_EDG OUT1_PE E CL_LVDS P 55 Programming Information 46 June 19, 2006 IDT82V3255 WAN PLL Table 34: Register List and Map (Continued) Address (Hex) 0B 7E Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reference Page P 56 P 57 0C 0D 0E 0F 10 11 12 16 17 18 19 1A 1D 23 24 25 27 28 MON_SW_PBO_CNFG - Frequency LOS_FLA FREQ_MO FREQ_MO ULTR_FAS PBO_FRE Monitor, Input Clock Selection & PBO G_TO_TD EXT_SW PBO_EN N_HARD_ N_CLK T_SW Z Control O EN PROTECTION_CNFG - Register ProPROTECTION_DATA[7:0] tection Mode Configuration Interrupt Registers INTERRUPT_CNFG - Interrupt ConfigHZ_EN INT_POL uration INTERRUPTS1_STS - Interrupt Status IN2_DIFF IN1_DIFF IN2_CMOS IN1_CMOS 1 T0_OPER T0_MAIN_ INTERRUPTS2_STS - Interrupt Status ATING_MO REF_FAIL IN3_CMOS 2 DE ED INTERRUPTS3_STS - Interrupt Status EX_SYNC INPUT_TO T4_STS 3 _ALARM _T4 INTERRUPTS1_ENABLE_CNFG IN2_DIFF IN1_DIFF IN2_CMOS IN1_CMOS Interrupt Control 1 T0_OPER T0_MAIN_ INTERRUPTS2_ENABLE_CNFG ATING_MO REF_FAIL IN3_CMOS Interrupt Control 2 DE ED INTERRUPTS3_ENABLE_CNFG - EX_SYNC INPUT_TO T4_STS Interrupt Control 3 _ALARM _T4 Input Clock Frequency & Priority Configuration Registers IN1_CMOS_CNFG - CMOS Input DIRECT_D LOCK_8K BUCKET_SEL[1:0] IN_FREQ[3:0] Clock 1 Configuration IV IN2_CMOS_CNFG - CMOS Input DIRECT_D LOCK_8K BUCKET_SEL[1:0] IN_FREQ[3:0] Clock 2 Configuration IV IN1_IN2_DIFF_HF_DIV_CNFG - Differential Input Clock 1 & 2 High Fre- IN2_DIFF_DIV[1:0] IN1_DIFF_DIV[1:0] quency Divider Configuration IN1_DIFF_CNFG - Differential Input DIRECT_D LOCK_8K BUCKET_SEL[1:0] IN_FREQ[3:0] Clock 1 Configuration IV IN2_DIFF_CNFG - Differential Input DIRECT_D LOCK_8K BUCKET_SEL[1:0] IN_FREQ[3:0] Clock 2 Configuration IV IN3_CMOS_CNFG - CMOS Input DIRECT_D LOCK_8K BUCKET_SEL[1:0] IN_FREQ[3:0] Clock 3 Configuration IV PRE_DIV_CH_CNFG - DivN Divider PRE_DIV_CH_VALUE[3:0] Channel Selection PRE_DIVN[7:0]_CNFG - DivN Divider PRE_DIVN_VALUE[7:0] Division Factor Configuration 1 PRE_DIVN[14:8]_CNFG DivN PRE_DIVN_VALUE[14:8] Divider Division Factor Configuration 2 IN1_IN2_CMOS_SEL_PRIORITY_CN FG - CMOS Input Clock 1 & 2 Priority IN2_CMOS_SEL_PRIORITY[3:0] IN1_CMOS_SEL_PRIORITY[3:0] Configuration * IN1_IN2_DIFF_SEL_PRIORITY_CNF G - Differential Input Clock 1 & 2 PriorIN2_DIFF_SEL_PRIORITY[3:0] IN1_DIFF_SEL_PRIORITY[3:0] ity Configuration * P 58 P 58 P 59 P 60 P 60 P 61 P 61 P 62 P 63 P 64 P 65 P 66 P 67 P 68 P 68 P 69 P 70 P 71 Programming Information 47 June 19, 2006 IDT82V3255 WAN PLL Table 34: Register List and Map (Continued) Address (Hex) 2A Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reference Page P 72 2E 2F 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40 IN3_CMOS_SEL_PRIORITY_CNFG CMOS Input Clock 3 Priority ConfiguIN3_CMOS_SEL_PRIORITY[3:0] ration * Input Clock Quality Monitoring Configuration & Status Registers FREQ_MON_FACTOR_CNFG - FacFREQ_MON_FACTOR[3:0] tor of Frequency Monitor Configuration ALL_FREQ_MON_THRESHOLD_CN FG - Frequency Monitor Threshold for ALL_FREQ_HARD_THRESHOLD[3:0] All Input Clocks Configuration UPPER_THRESHOLD_0_CNFG Upper Threshold for Leaky Bucket UPPER_THRESHOLD_0_DATA[7:0] Configuration 0 LOWER_THRESHOLD_0_CNFG Lower Threshold for Leaky Bucket LOWER_THRESHOLD_0_DATA[7:0] Configuration 0 BUCKET_SIZE_0_CNFG - Bucket BUCKET_SIZE_0_DATA[7:0] Size for Leaky Bucket Configuration 0 DECAY_RATE_0_CNFG - Decay Rate DECAY_RATE_0_DATA for Leaky Bucket Configuration 0 [1:0] UPPER_THRESHOLD_1_CNFG Upper Threshold for Leaky Bucket UPPER_THRESHOLD_1_DATA[7:0] Configuration 1 LOWER_THRESHOLD_1_CNFG Lower Threshold for Leaky Bucket LOWER_THRESHOLD_1_DATA[7:0] Configuration 1 BUCKET_SIZE_1_CNFG - Bucket BUCKET_SIZE_1_DATA[7:0] Size for Leaky Bucket Configuration 1 DECAY_RATE_1_CNFG - Decay Rate DECAY_RATE_1_DATA for Leaky Bucket Configuration 1 [1:0] UPPER_THRESHOLD_2_CNFG Upper Threshold for Leaky Bucket UPPER_THRESHOLD_2_DATA[7:0] Configuration 2 LOWER_THRESHOLD_2_CNFG Lower Threshold for Leaky Bucket LOWER_THRESHOLD_2_DATA[7:0] Configuration 2 BUCKET_SIZE_2_CNFG - Bucket BUCKET_SIZE_2_DATA[7:0] Size for Leaky Bucket Configuration 2 DECAY_RATE_2_DATA DECAY_RATE_2_CNFG - Decay Rate [1:0] for Leaky Bucket Configuration 2 UPPER_THRESHOLD_3_CNFG Upper Threshold for Leaky Bucket UPPER_THRESHOLD_3_DATA[7:0] Configuration 3 LOWER_THRESHOLD_3_CNFG Lower Threshold for Leaky Bucket LOWER_THRESHOLD_3_DATA[7:0] Configuration 3 BUCKET_SIZE_3_CNFG - Bucket BUCKET_SIZE_3_DATA[7:0] Size for Leaky Bucket Configuration 3 DECAY_RATE_3_CNFG - Decay Rate DECAY_RATE_3_DATA [1:0] for Leaky Bucket Configuration 3 P 73 P 73 P 74 P 74 P 74 P 75 P 75 P 75 P 76 P 76 P 76 P 77 P 77 P 77 P 78 P 78 P 78 P 79 Programming Information 48 June 19, 2006 IDT82V3255 WAN PLL Table 34: Register List and Map (Continued) Address (Hex) 41 42 Register Name IN_FREQ_READ_CH_CNFG - Input Clock Frequency Read Channel Selection IN_FREQ_READ_STS - Input Clock Frequency Read Value IN1_IN2_CMOS_STS - CMOS Input Clock 1 & 2 Status Bit 7 Bit 6 Bit 5 Bit 4 IN_FREQ_VALUE[7:0] IN2_CMOS _FREQ_H ARD_ALA RM IN2_DIFF_ FREQ_HA RD_ALAR M IN2_CMOS _NO_ACTI VITY_ALA RM IN2_DIFF_ NO_ACTIV ITY_ALAR M IN2_CMOS _PH_LOC K_ALARM IN2_DIFF_ PH_LOCK _ALARM IN1_CMOS _FREQ_H ARD_ALA RM IN1_DIFF_ FREQ_HA RD_ALAR M IN3_CMOS _FREQ_H ARD_ALA RM IN1_CMOS _NO_ACTI VITY_ALA RM IN1_DIFF_ NO_ACTIV ITY_ALAR M IN3_CMOS _NO_ACTI VITY_ALA RM IN1_CMOS _PH_LOC K_ALARM IN1_DIFF_ PH_LOCK _ALARM IN3_CMOS _PH_LOC K_ALARM Bit 3 Bit 2 Bit 1 Bit 0 Reference Page P 79 P 80 IN_FREQ_READ_CH[3:0] 44 - - P 81 45 IN1_IN2_DIFF_STS - Differential Input Clock 1 & 2 Status - - P 82 47 IN3_CMOS_STS - CMOS Input Clock 3 Status - - - P 83 4A 4B 4E 4F 50 51 52 53 54 55 56 57 58 T0 / T4 DPLL Input Clock Selection Registers INPUT_VALID1_STS - Input Clocks IN2_DIFF IN1_DIFF IN2_CMOS IN1_CMOS Validity 1 INPUT_VALID2_STS - Input Clocks IN3_CMOS Validity 2 PRIORITY_TABLE1_STS - Priority HIGHEST_PRIORITY_VALIDATED[3:0] CURRENTLY_SELECTED_INPUT[3:0] Status 1 * PRIORITY_TABLE2_STS - Priority SECOND_HIGHEST_PRIORITY_VALIDATED[3:0 THIRD_HIGHEST_PRIORITY_VALIDATED[3:0] Status 2 * ] T0_INPUT_SEL_CNFG - T0 Selected T0_INPUT_SEL[3:0] Input Clock Configuration T4_LOCK_ T0_FOR_T T4_TEST_ T4_INPUT_SEL_CNFG - T4 Selected T4_INPUT_SEL[3:0] T0 4 T0_PH Input Clock Configuration T0 / T4 DPLL State Machine Control Registers EX_SYNC T0_DPLL_ T4_DPLL_ OPERATING_STS - DPLL Operating T4_DPLL_ T0_DPLL_ _ALARM_ T0_DPLL_OPERATING_MODE[2:0] SOFT_FRE SOFT_FRE Status LOCK LOCK MON Q_ALARM Q_ALRAM T0_OPERATING_MODE_CNFG - T0 T0_OPERATING_MODE[2:0] DPLL Operating Mode Configuration T4_OPERATING_MODE_CNFG - T4 T4_OPERATING_MODE[2:0] DPLL Operating Mode Configuration T0 / T4 DPLL & APLL Configuration Registers T0_DPLL_APLL_PATH_CNFG - T0 T0_GSM_OBSAI_16E1 T0_12E1_24T1_E3_T3 T0_APLL_PATH[3:0] DPLL & APLL Path Configuration _16T1_SEL[1:0] _SEL[1:0] T0_DPLL_START_BW_DAMPING_C NFG - T0 DPLL Start Bandwidth & T0_DPLL_START_DAMPING[2:0] T0_DPLL_START_BW[4:0] Damping Factor Configuration T0_DPLL_ACQ_BW_DAMPING_CNF G - T0 DPLL Acquisition Bandwidth & T0_DPLL_ACQ_DAMPING[2:0] T0_DPLL_ACQ_BW[4:0] Damping Factor Configuration T0_DPLL_LOCKED_BW_DAMPING_ CNFG - T0 DPLL Locked Bandwidth & T0_DPLL_LOCKED_DAMPING[2:0] T0_DPLL_LOCKED_BW[4:0] Damping Factor Configuration P 84 P 84 P 85 P 86 P 86 P 87 P 88 P 89 P 89 P 90 P 91 P 92 P 93 Programming Information 49 June 19, 2006 IDT82V3255 WAN PLL Table 34: Register List and Map (Continued) Address (Hex) 59 Register Name T0_BW_OVERSHOOT_CNFG - T0 DPLL Bandwidth Overshoot Configuration PHASE_LOSS_COARSE_LIMIT_CNF G - Phase Loss Coarse Detector Limit Configuration * PHASE_LOSS_FINE_LIMIT_CNFG Phase Loss Fine Detector Limit Configuration * T0_HOLDOVER_MODE_CNFG - T0 DPLL Holdover Mode Configuration T0_HOLDOVER_FREQ[7:0]_CNFG T0 DPLL Holdover Frequency Configuration 1 T0_HOLDOVER_FREQ[15:8]_CNFG - T0 DPLL Holdover Frequency Configuration 2 T0_HOLDOVER_FREQ[23:16]_CNFG - T0 DPLL Holdover Frequency Configuration 3 T4_DPLL_APLL_PATH_CNFG - T4 DPLL & APLL Path Configuration T4_DPLL_LOCKED_BW_DAMPING_ CNFG - T4 DPLL Locked Bandwidth & Damping Factor Configuration CURRENT_DPLL_FREQ[7:0]_STS DPLL Current Frequency Status 1 * CURRENT_DPLL_FREQ[15:8]_STS DPLL Current Frequency Status 2 * CURRENT_DPLL_FREQ[23:16]_STS - DPLL Current Frequency Status 3 * DPLL_FREQ_SOFT_LIMIT_CNFG DPLL Soft Limit Configuration DPLL_FREQ_HARD_LIMIT[7:0]_CNF G - DPLL Hard Limit Configuration 1 DPLL_FREQ_HARD_LIMIT[15:8]_CN FG - DPLL Hard Limit Configuration 2 CURRENT_DPLL_PHASE[7:0]_STS DPLL Current Phase Status 1 * CURRENT_DPLL_PHASE[15:8]_STS - DPLL Current Phase Status 2 * T0_T4_APLL_BW_CNFG - T0 / T4 APLL Bandwidth Configuration OUT2_FREQ_CNFG - Output Clock 2 Frequency Configuration OUT1_FREQ_CNFG - Output Clock 1 Frequency Configuration OUT1_INV_CNFG - Output Clock 1 Invert Configuration Bit 7 AUTO_BW _SEL Bit 6 Bit 5 Bit 4 Bit 3 T0_LIMT Bit 2 Bit 1 Bit 0 Reference Page P 93 5A 5B 5C 5D COARSE_ MULTI_PH MULTI_PH PH_LOS_L WIDE_EN _8K_4K_2 PH_LOS_COARSE_LIMT[3:0] _APP IMT_EN K_EN FINE_PH_ FAST_LOS LOS_LIMT PH_LOS_FINE_LIMT[2:0] _SW _EN MAN_HOL AUTO_AV READ_AV TEMP_HOLDOVER_M FAST_AVG DOVER G G ODE[1:0] T0_HOLDOVER_FREQ[7:0] P 94 P 95 P 96 P 96 5E T0_HOLDOVER_FREQ[15:8] P 97 5F 60 61 62 63 64 65 66 67 68 69 6A T0_HOLDOVER_FREQ[23:16] T4_APLL_PATH[3:0] T4_DPLL_LOCKED_DAMPING[2:0] T4_GSM_GPS_16E1_1 T4_12E1_24T1_E3_T3 6T1_SEL[1:0] _SEL[1:0] T4_DPLL_LOCKED_B W[1:0] P 97 P 98 P 99 P 99 P 99 P 100 P 100 P 100 P 101 P 101 P 101 T4_APLL_BW[1:0] P 102 CURRENT_DPLL_FREQ[7:0] CURRENT_DPLL_FREQ[15:8] CURRENT_DPLL_FREQ[23:16] FREQ_LIM T_PH_LOS DPLL_FREQ_SOFT_LIMT[6:0] DPLL_FREQ_HARD_LIMT[7:0] DPLL_FREQ_HARD_LIMT[15:8] CURRENT_PH_DATA[7:0] CURRENT_PH_DATA[15:8] T0_APLL_BW[1:0] - Output Configuration Registers 6D 71 72 OUT2_PATH_SEL[3:0] OUT1_PATH_SEL[3:0] OUT2_DIVIDER[3:0] OUT1_DIVIDER[3:0] OUT1_INV P 103 P 104 P 104 Programming Information 50 June 19, 2006 IDT82V3255 WAN PLL Table 34: Register List and Map (Continued) Address (Hex) 73 74 Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reference Page P 105 P 106 78 7A 7B 7C 7D OUT2_INV_CNFG - Output Clock 2 OUT2_INV Invert Configuration FR_MFR_SYNC_CNFG - Frame Sync 2K_8K_PU IN_2K_4K_ & Multiframe Sync Output Configura8K_EN 2K_EN L_POSITI 8K_INV 8K_PUL 2K_INV 2K_PUL 8K_INV tion ON PBO & Phase Offset Control Registers PHASE_MON_PBO_CNFG - Phase IN_NOISE PH_MON_ PH_MON_ Transient Monitor & PBO ConfiguraPH_TR_MON_LIMT[3:0] _WINDOW EN PBO_EN tion PHASE_OFFSET[7:0]_CNFG - Phase PH_OFFSET[7:0] Offset Configuration 1 PHASE_OFFSET[9:8]_CNFG - Phase PH_OFFS PH_OFFSET[9:8] Offset Configuration 2 ET_EN Synchronization Configuration Registers SYNC_MONITOR_CNFG - Sync Mon- SYNC_BY SYNC_MON_LIMT[2:0] itor Configuration PASS SYNC_PHASE_CNFG - Sync Phase SYNC_PH3[1:0] SYNC_PH2[1:0] SYNC_PH1[1:0] Configuration P 107 P 107 P 108 P 109 P 110 6.2 6.2.1 REGISTER DESCRIPTION GLOBAL CONTROL REGISTERS ID[7:0] - Device ID 1 Address: 00H Type: Read Default Value: 10001000 7 ID7 Bit 7-0 Name ID[7:0] Refer to the description of the ID[15:8] bits (b7~0, 01H). 6 ID6 5 ID5 4 ID4 3 ID3 Description 2 ID2 1 ID1 0 ID0 ID[15:8] - Device ID 2 Address: 01H Type: Read Default Value: 00010001 7 ID15 Bit 7-0 6 ID14 Name ID[15:8] 5 ID13 4 ID12 3 ID11 Description The value in the ID[15:0] bits are pre-set, representing the identification number for the IDT82V3255. 2 ID10 1 ID9 0 ID8 Programming Information 51 June 19, 2006 IDT82V3255 WAN PLL NOMINAL_FREQ[7:0]_CNFG - Crystal Oscillator Frequency Offset Calibration Configuration 1 Address: 04H Type: Read / Write Default Value: 00000000 7 NOMINAL_FRE Q_VALUE7 Bit 7-0 6 NOMINAL_FRE Q_VALUE6 Name 5 NOMINAL_FRE Q_VALUE5 4 NOMINAL_FRE Q_VALUE4 3 NOMINAL_FRE Q_VALUE3 2 NOMINAL_FRE Q_VALUE2 1 NOMINAL_FRE Q_VALUE1 0 NOMINAL_FRE Q_VALUE0 Description NOMINAL_FREQ_VALUE[7:0] Refer to the description of the NOMINAL_FREQ_VALUE[23:16] bits (b7~0, 06H). NOMINAL_FREQ[15:8]_CNFG - Crystal Oscillator Frequency Offset Calibration Configuration 2 Address: 05H Type: Read / Write Default Value: 00000000 7 NOMINAL_FRE Q_VALUE15 Bit 7-0 6 NOMINAL_FRE Q_VALUE14 Name 5 NOMINAL_FRE Q_VALUE13 4 NOMINAL_FRE Q_VALUE12 3 NOMINAL_FRE Q_VALUE11 2 NOMINAL_FRE Q_VALUE10 1 NOMINAL_FRE Q_VALUE9 0 NOMINAL_FRE Q_VALUE8 Description NOMINAL_FREQ_VALUE[15:8] Refer to the description of the NOMINAL_FREQ_VALUE[23:16] bits (b7~0, 06H). NOMINAL_FREQ[23:16]_CNFG - Crystal Oscillator Frequency Offset Calibration Configuration 3 Address: 06H Type: Read / Write Default Value: 00000000 7 NOMINAL_FRE Q_VALUE23 Bit 6 NOMINAL_FRE Q_VALUE22 Name 5 NOMINAL_FRE Q_VALUE21 4 NOMINAL_FRE Q_VALUE20 3 NOMINAL_FRE Q_VALUE19 2 NOMINAL_FRE Q_VALUE18 1 NOMINAL_FRE Q_VALUE17 0 NOMINAL_FRE Q_VALUE16 Description 7-0 The NOMINAL_FREQ_VALUE[23:0] bits represent a 2's complement signed integer. If the value is multiplied by 0.0000884, the calibration value for the master clock in ppm will be gotten. For example, the frequency offset on OSCI is +3 ppm. Though -3 ppm should be compensated, the calibration value is NOMINAL_FREQ_VALUE[23:16] calculated as +3 ppm: 3 / 0.0000884 = 33937 (Dec.) = 8490 (Hex); So `008490' should be written into these bits. The calibration range is within 741 ppm. Programming Information 52 June 19, 2006 IDT82V3255 WAN PLL T4_T0_REG_SEL_CNFG - T0 / T4 Registers Selection Configuration Address: 07H Type: Read / Write Default Value: XXX0XXXX 7 Bit 7-5 4 3-0 Name T4_T0_SEL 6 5 4 T4_T0_SEL 3 Description Reserved. A part of the registers are shared by T0 and T4 paths. These registers are addressed 27H, 28H, 2AH, 4EH, 4FH, 5AH, 5BH, 62H ~ 64H, 68H and 69H. This bit determines whether the register configuration is available for T0 or T4 path. 0: T0 path (default). 1: T4 path. Reserved. 2 1 0 - PHASE_ALARM_TIME_OUT_CNFG - Phase Lock Alarm Time-Out Configuration Address: 08H Type: Read / Write Default Value: 00110010 7 MULTI_FACTO R1 Bit 6 MULTI_FACTO R0 Name 5 TIME_OUT_VA LUE5 4 TIME_OUT_VA LUE4 3 TIME_OUT_VA LUE3 2 TIME_OUT_VA LUE2 1 TIME_OUT_VA LUE1 0 TIME_OUT_VAL UE0 Description 7-6 5-0 These bits determine a factor which has a relationship with a period in seconds. A phase lock alarm will be raised if the T0 selected input clock is not locked in T0 DPLL within this period. If the PH_ALARM_TIMEOUT bit (b5, 09H) is `1', the phase lock alarm will be cleared after this period (starting from when the alarm is raised). Refer to the description of the TIME_OUT_VALUE[5:0] bits (b5~0, 08H). MULTI_FACTOR[1:0] 00: 2 (default) 01: 4 10: 8 11: 16 These bits represent an unsigned integer. If the value in these bits is multiplied by the value in the MULTI_FACTOR[1:0] bits (b7~6, 08H), a period in seconds will be gotten. TIME_OUT_VALUE[5:0] A phase lock alarm will be raised if the T0 selected input clock is not locked in T0 DPLL within this period. If the PH_ALARM_TIMEOUT bit (b5, 09H) is `1', the phase lock alarm will be cleared after this period (starting from when the alarm is raised). Programming Information 53 June 19, 2006 IDT82V3255 WAN PLL INPUT_MODE_CNFG - Input Mode Configuration Address: 09H Type: Read / Write Default Value: 10100X10 7 AUTO_EXT_SY NC_EN Bit 7 6 EXT_SYNC_EN 5 PH_ALARM_TI MEOUT 4 SYNC_FREQ1 3 SYNC_FREQ0 2 IN_SONET_SD H 1 0 REVERTIVE_M ODE Name AUTO_EXT_SYNC_EN Description This bit is valid only when the SYNC_BYPASS bit (b7, 7CH) is `0'. Refer to the description of the EXT_SYNC_EN bit (b6, 09H). This bit is valid only when the SYNC_BYPASS bit (b7, 7CH) is `0'. This bit, together with the AUTO_EXT_SYNC_EN bit (b7, 09H), determines whether the selected frame sync input signal is enabled to synchronize the frame sync output signals. AUTO_EXT_SYNC_EN don't-care 0 1 EXT_SYNC_EN 0 1 1 Synchronization Disabled (default) Enabled Disabled 6 EXT_SYNC_EN 5 4-3 2 1 0 This bit determines how to clear the phase lock alarm. 0: The phase lock alarm will be cleared when a `1' is written to the corresponding INn_CMOS_PH_LOCK_ALARM (n = 1, 2 PH_ALARM_TIMEOUT or 3) / INn_DIFF_PH_LOCK_ALARM (n = 1 or 2) bit (b4/0, 44H/45H/47H). 1: The phase lock alarm will be cleared after a period (= TIME_OUT_VALUE[5:0] (b5~0, 08H) X MULTI_FACTOR[1:0] (b7~6, 08H) in second) which starts from when the alarm is raised. (default) These bits set the frequency of the frame sync signals input on the EX_SYNC1 ~ EX_SYNC3 pins. 00: 8 kHz (default) SYNC_FREQ[1:0] 01: 8 kHz. 10: 4 kHz. 11: 2 kHz. This bit selects the SDH or SONET network type. 0: SDH. The DPLL required clock is 2.048 MHz when the IN_FREQ[3:0] bits (b3~0, 16H, 17H, 19H, 1AH & 1DH) are `0001' and the T0/T4 DPLL output from the 16E1/16T1 path is 16E1. IN_SONET_SDH 1: SONET. The DPLL required clock is 1.544 MHz when the IN_FREQ[3:0] bits (b3~0, 16H, 17H, 19H, 1AH & 1DH) are `0001' and the T0/T4 DPLL output from the 16E1/16T1 path is 16T1. The default value of this bit is determined by the SONET/SDH pin during reset. Reserved. This bit selects Revertive or Non-Revertive switch for T0 path. REVERTIVE_MODE 0: Non-Revertive switch. (default) 1: Revertive switch. Programming Information 54 June 19, 2006 IDT82V3255 WAN PLL DIFFERENTIAL_IN_OUT_OSCI_CNFG - Differential Input / Output Port & Master Clock Configuration Address: 0AH Type: Read / Write Default Value: XXXXX00X 7 Bit 7-3 2 6 Name Reserved. This bit selects a better active edge of the master clock. OSC_EDGE 0: The rising edge. (default) 1: The falling edge. This bit selects a port technology for OUT1. OUT1_PECL_LVDS 0: LVDS. (default) 1: PECL. Reserved 5 4 3 2 OSC_EDGE Description 1 OUT1_PECL_LVDS 0 - 1 0 Programming Information 55 June 19, 2006 IDT82V3255 WAN PLL MON_SW_PBO_CNFG - Frequency Monitor, Input Clock Selection & PBO Control Address: 0BH Type: Read / Write Default Value: 100X01X1 7 FREQ_MON_C LK Bit 7 6 LOS_FLAG_TO _TDO Name FREQ_MON_CLK 5 ULTR_FAST_SW 4 EXT_SW 3 PBO_FREZ 2 PBO_EN 1 0 FREQ_MON_H ARD_EN Description 6 5 4 3 2 1 0 The bit selects a reference clock for input clock frequency monitoring. 0: The output of T0 DPLL. 1: The master clock. (default) The bit determines whether the interrupt of T0 selected input clock fail - is reported by the TDO pin. 0: Not reported. TDO pin is used as JTAG test data output which complies with IEEE 1149.1. (default) LOS_FLAG_TO_TDO 1: Reported. TDO pin mimics the state of the T0_MAIN_REF_FAILED bit (b6, 0EH) and does not strictly comply with IEEE 1149.1. This bit determines whether the T0 selected input clock is valid when missing 2 consecutive clock cycles or more. ULTR_FAST_SW 0: Valid. (default) 1: Invalid. This bit determines the T0 input clock selection. 0: Forced selection or Automatic selection, as controlled by the T0_INPUT_SEL[3:0] bits (b3~0, 50H). EXT_SW 1: External Fast selection. The default value of this bit is determined by the FF_SRCSW pin during reset. This bit is valid only when the PBO is enabled by the PBO_EN bit (b2, 0BH). It determines whether PBO is frozen at the current phase offset when a PBO event is triggered. PBO_FREZ 0: Not frozen. (default) 1: Frozen. Further PBO events are ignored and the current phase offset is maintained. This bit determines whether PBO is enabled when the T0 selected input clock switch or the T0 DPLL exiting from Holdover mode or Free-Run mode occurs. PBO_EN 0: Disabled. 1: Enabled. (default) Reserved. This bit determines whether the frequency hard alarm is enabled when the frequency of the input clock with respect to the reference clock is above the frequency hard alarm threshold. The reference clock can be the output of T0 DPLL or the masFREQ_MON_HARD_EN ter clock, as determined by the FREQ_MON_CLK bit (b7, 0BH). 0: Disabled. 1: Enabled. (default) Programming Information 56 June 19, 2006 IDT82V3255 WAN PLL PROTECTION_CNFG - Register Protection Mode Configuration Address: 7EH Type: Read / Write Default Value: 10000101 7 PROTECTION_ DATA7 Bit 6 PROTECTION_ DATA6 Name 5 PROTECTION_ DATA5 4 PROTECTION_ DATA4 3 PROTECTION_ DATA3 2 PROTECTION_ DATA2 1 PROTECTION_ DATA1 0 PROTECTION_ DATA0 Description 7-0 These bits select a register write protection mode. 00000000 - 10000100, 10000111 - 11111111: Protected mode. No other registers can be written except this register. PROTECTION_DATA[7:0] 10000101: Fully Unprotected mode. All the writable registers can be written. (default) 10000110: Single Unprotected mode. One more register can be written besides this register. After write operation (not including writing a `1' to clear the bit to `0'), the device automatically switches to Protected mode. Programming Information 57 June 19, 2006 IDT82V3255 WAN PLL 6.2.2 INTERRUPT REGISTERS INTERRUPT_CNFG - Interrupt Configuration Address: 0CH Type: Read / Write Default Value: XXXXXX10 7 Bit 7-2 1 Name HZ_EN 6 5 4 3 Description Reserved. This bit determines the output characteristics of the INT_REQ pin. 0: The output on the INT_REQ pin is high/low when the interrupt is active; the output is the opposite when the interrupt is inactive. 1: The output on the INT_REQ pin is high/low when the interrupt is active; the output is in high impedance state when the interrupt is inactive. (default) This bit determines the active level on the INT_REQ pin for an active interrupt indication. 0: Active low. (default) 1: Active high. 2 1 HZ_EN 0 INT_POL 0 INT_POL INTERRUPTS1_STS - Interrupt Status 1 Address: 0DH Type: Read / Write Default Value: XX1111XX 7 Bit 7-6 Name 6 5 IN2_DIFF 4 IN1_DIFF 3 IN2_CMOS 2 IN1_CMOS 1 0 - Description Reserved. This bit indicates the validity changes (from `valid' to `invalid' or from `invalid' to `valid') for the corresponding INn_DIFF; i.e., whether there is a transition (from `0' to `1' or from `1' to `0') on the corresponding INn_DIFF bit (b5/4, 4AH). Here n is 2 or 1. 0: Has not changed. 1: Has changed. (default) This bit is cleared by writing a `1'. This bit indicates the validity changes (from `valid' to `invalid' or from `invalid' to `valid') for the corresponding INn_CMOS; i.e., whether there is a transition (from `0' to `1' or from `1' to `0') on the corresponding INn_CMOS bit (b3/2, 4AH). Here n is 2 or 1. 0: Has not changed. 1: Has changed. (default) This bit is cleared by writing a `1'. Reserved. 5-4 INn_DIFF 3-2 INn_CMOS 1-0 - Programming Information 58 June 19, 2006 IDT82V3255 WAN PLL INTERRUPTS2_STS - Interrupt Status 2 Address: 0EH Type: Read / Write Default Value: 00XXXXX1 7 T0_OPERATING _MODE Bit 6 T0_MAIN_REF_F AILED Name 5 4 3 Description 2 1 0 IN3_CMOS 7 6 5-1 0 This bit indicates the operating mode switch for T0 DPLL; i.e., whether the value in the T0_DPLL_OPERATING_MODE[2:0] bits (b2~0, 52H) changes. T0_OPERATING_MODE 0: Has not switched. (default) 1: Has switched. This bit is cleared by writing a `1'. This bit indicates whether the T0 selected input clock has failed. The T0 selected input clock fails when its validity changes from `valid' to `invalid'; i.e., when there is a transition from `1' to `0' on the corresponding INn_CMOS / INn_DIFF bit (4AH, 4BH). T0_MAIN_REF_FAILED 0: Has not failed. (default) 1: Has failed. This bit is cleared by writing a `1'. Reserved. This bit indicates the validity changes (from `valid' to `invalid' or from `invalid' to `valid') for IN3_CMOS for T0 path, i.e., whether there is a transition (from `0' to `1' or from `1' to `0') on the corresponding IN3_CMOS bit (b0, 4BH). IN3_CMOS 0: Has not changed. 1: Has changed. (default) This bit is cleared by writing a `1'. Programming Information 59 June 19, 2006 IDT82V3255 WAN PLL INTERRUPTS3_STS - Interrupt Status 3 Address: 0FH Type: Read / Write Default Value: 11X1XXXX 7 EX_SYNC_ALARM Bit 6 T4_STS Name 5 4 INPUT_TO_T4 3 Description 2 1 0 - 7 6 5 4 3-0 This bit indicates whether an external sync alarm is raised; i.e., whether there is a transition from `0' to `1' on the EX_SYNC_ALARM_MON bit (b7, 52H). EX_SYNC_ALARM 0: Has not occurred. 1: Has occurred. (default) This bit is cleared by writing a `1'. This bit indicates the T4 DPLL locking status changes (from `locked' to `unlocked' or from `unlocked' to `locked'); i.e., whether there is a transition (from `0' to `1' or from `1' to `0') on the T4_DPLL_LOCK bit (b6, 52H). T4_STS 0: Has not changed. 1: Has changed. (default) This bit is cleared by writing a `1'. Reserved. This bit indicates whether all the input clocks for T4 path changes to be unqualified; i.e., whether the HIGHEST_PRIORITY_VALIDATED[3:0] bits (b7~4, 4EH) are set to `0000' when these bits are available for T4 path. INPUT_TO_T4 0: Has not changed. 1: Has changed. (default) This bit is cleared by writing a `1'. Reserved. INTERRUPTS1_ENABLE_CNFG - Interrupt Control 1 Address: 10H Type: Read / Write Default Value: XX0000XX 7 Bit 7-6 5-4 Name INn_DIFF 6 5 IN2_DIFF 4 IN1_DIFF 3 IN2_CMOS Description Reserved. This bit controls whether the interrupt is enabled to be reported on the INT_REQ pin when the input clock validity changes (from `valid' to `invalid' or from `invalid' to `valid'), i.e., when the corresponding INn_DIFF bit (b5/4, 0DH) is `1'. Here n is 2 or 1. 0: Disabled. (default) 1: Enabled. This bit controls whether the interrupt is enabled to be reported on the INT_REQ pin when the input clock validity changes (from `valid' to `invalid' or from `invalid' to `valid'), i.e., when the corresponding INn_CMOS bit (b3/2, 0DH) is `1'. Here n is 2 or 1. 0: Disabled. (default) 1: Enabled. Reserved. 2 IN1_CMOS 1 0 - 3-2 1-0 INn_CMOS - Programming Information 60 June 19, 2006 IDT82V3255 WAN PLL INTERRUPTS2_ENABLE_CNFG - Interrupt Control 2 Address: 11H Type: Read / Write Default Value:00XXXXX0 7 T0_OPERATING _MODE Bit 7 6 T0_MAIN_REF_F AILED Name 5 4 3 Description 2 1 0 IN3_CMOS 6 5-1 0 This bit controls whether the interrupt is enabled to be reported on the INT_REQ pin when the T0 DPLL operating mode switches, i.e., when the T0_OPERATING_MODE bit (b7, 0EH) is `1'. T0_OPERATING_MODE 0: Disabled. (default) 1: Enabled. This bit controls whether the interrupt is enabled to be reported on the INT_REQ pin when the T0 selected input clock has failed; i.e., when the T0_MAIN_REF_FAILED bit (b6, 0EH) is `1'. T0_MAIN_REF_FAILED 0: Disabled. (default) 1: Enabled. Reserved. This bit controls whether the interrupt is enabled to be reported on the INT_REQ pin when the input clock validity changes (from `valid' to `invalid' or from `invalid' to `valid'), i.e., when the corresponding IN3_CMOS bit (b0, 0EH) is `1'. IN3_CMOS 0: Disabled. (default) 1: Enabled. INTERRUPTS3_ENABLE_CNFG - Interrupt Control 3 Address: 12H Type: Read / Write Default Value: 00X0XXXX 7 EX_SYNC_ALARM Bit 7 6 T4_STS Name 5 4 INPUT_TO_T4 3 Description 2 1 0 - 6 5 4 3-0 This bit controls whether the interrupt is enabled to be reported on the INT_REQ pin when an external sync alarm has occurred, i.e., when the EX_SYNC_ALARM bit (b7, 0FH) is `1'. EX_SYNC_ALARM 0: Disabled. (default) 1: Enabled. This bit controls whether the interrupt is enabled to be reported on the INT_REQ pin when the T4 DPLL locking status changes (from `locked' to `unlocked' or from `unlocked' to `locked'), i.e., when the T4_STS bit (b6, 0FH) is `1'. T4_STS 0: Disabled. (default) 1: Enabled. Reserved. This bit controls whether the interrupt is enabled to be reported on the INT_REQ pin when all the input clocks for T4 path change to be unqualified, i.e., when the INPUT_TO_T4 bit (b4, 0FH) is `1'. INPUT_TO_T4 0: Disabled. (default) 1: Enabled. Reserved. Programming Information 61 June 19, 2006 IDT82V3255 WAN PLL 6.2.3 INPUT CLOCK FREQUENCY & PRIORITY CONFIGURATION REGISTERS IN1_CMOS_CNFG - CMOS Input Clock 1 Configuration Address: 16H Type: Read / Write Default Value: 00000000 7 DIRECT_DIV Bit 7 6 LOCK_8K Name DIRECT_DIV 5 BUCKET_SEL1 4 BUCKET_SEL0 3 IN_FREQ3 2 IN_FREQ2 1 IN_FREQ1 0 IN_FREQ0 Description Refer to the description of the LOCK_8K bit (b6, 16H). This bit, together with the DIRECT_DIV bit (b7, 16H), determines whether the DivN Divider or the Lock 8k Divider is used for IN1_CMOS: DIRECT_DIV bit LOCK_8K bit 0 1 0 1 Used Divider Both bypassed (default) Lock 8k Divider DivN Divider Reserved 6 LOCK_8K 0 0 1 1 5-4 3-0 These bits select one of the four groups of leaky bucket configuration registers for IN1_CMOS: 00: Group 0; the addresses of the configuration registers are 31H ~ 34H. (default) BUCKET_SEL[1:0] 01: Group 1; the addresses of the configuration registers are 35H ~ 38H. 10: Group 2; the addresses of the configuration registers are 39H ~ 3CH. 11: Group 3; the addresses of the configuration registers are 3DH ~ 40H. These bits set the DPLL required frequency for IN1_CMOS: 0000: 8 kHz. (default) 0001: 1.544 MHz (when the IN_SONET_SDH bit (b2, 09H) is `1') / 2.048 MHz (when the IN_SONET_SDH bit (b2, 09H) is `0'). 0010: 6.48 MHz. 0011: 19.44 MHz. 0100: 25.92 MHz. IN_FREQ[3:0] 0101: 38.88 MHz. 0110 ~ 1000: Reserved. 1001: 2 kHz. 1010: 4 kHz. 1011 ~ 1111: Reserved. For IN1_CMOS, the required frequency should not be set higher than that of the input clock. Programming Information 62 June 19, 2006 IDT82V3255 WAN PLL IN2_CMOS_CNFG - CMOS Input Clock 2 Configuration Address: 17H Type: Read / Write Default Value: 00000000 7 DIRECT_DIV Bit 7 6 LOCK_8K Name DIRECT_DIV 5 BUCKET_SEL1 4 BUCKET_SEL0 3 IN_FREQ3 2 IN_FREQ2 1 IN_FREQ1 0 IN_FREQ0 Description Refer to the description of the LOCK_8K bit (b6, 17H). This bit, together with the DIRECT_DIV bit (b7, 17H), determines whether the DivN Divider or the Lock 8k Divider is used for IN2_CMOS: DIRECT_DIV bit LOCK_8K bit 0 1 0 1 Used Divider Both bypassed (default) Lock 8k Divider DivN Divider Reserved 6 LOCK_8K 0 0 1 1 5-4 3-0 These bits select one of the four groups of leaky bucket configuration registers for IN2_CMOS: 00: Group 0; the addresses of the configuration registers are 31H ~ 34H. (default) BUCKET_SEL[1:0] 01: Group 1; the addresses of the configuration registers are 35H ~ 38H. 10: Group 2; the addresses of the configuration registers are 39H ~ 3CH. 11: Group 3; the addresses of the configuration registers are 3DH ~ 40H. These bits set the DPLL required frequency for IN2_CMOS: 0000: 8 kHz. (default) 0001: 1.544 MHz (when the IN_SONET_SDH bit (b2, 09H) is `1') / 2.048 MHz (when the IN_SONET_SDH bit (b2, 09H) is `0'). 0010: 6.48 MHz. 0011: 19.44 MHz. 0100: 25.92 MHz. IN_FREQ[3:0] 0101: 38.88 MHz. 0110 ~ 1000: Reserved. 1001: 2 kHz. 1010: 4 kHz. 1011 ~ 1111: Reserved. For the IN2_CMOS, the required frequency should not be set higher than that of the input clock. Programming Information 63 June 19, 2006 IDT82V3255 WAN PLL IN1_IN2_DIFF_HF_DIV_CNFG - Differential Input Clock 1 & 2 High Frequency Divider Configuration Address: 18H Type: Read / Write Default Value: 00XXXX00 7 IN2_DIFF_DIV1 Bit 6 IN2_DIFF_DIV0 Name 5 4 3 Description These bits determine whether the HF Divider is used and what the division factor is for IN2_DIFF frequency division: 00: Bypassed. (default) 01: Divided by 4. 10: Divided by 5. 11: Reserved. Reserved. These bits determine whether the HF Divider is used and what the division factor is for IN1_DIFF frequency division: 00: Bypassed. (default) 01: Divided by 4. 10: Divided by 5. 11: Reserved. 2 1 IN1_DIFF_DIV1 0 IN1_DIFF_DIV0 7-6 IN2_DIFF_DIV[1:0] 5-2 - 1-0 IN1_DIFF_DIV[1:0] Programming Information 64 June 19, 2006 IDT82V3255 WAN PLL IN1_DIFF_CNFG - Differential Input Clock 1 Configuration Address: 19H Type: Read / Write Default Value: 00000011 7 DIRECT_DIV Bit 7 6 LOCK_8K Name DIRECT_DIV 5 BUCKET_SEL1 4 BUCKET_SEL0 3 IN_FREQ3 2 IN_FREQ2 1 IN_FREQ1 0 IN_FREQ0 Description Refer to the description of the LOCK_8K bit (b6, 19H). This bit, together with the DIRECT_DIV bit (b7, 19H), determines whether the DivN Divider or the Lock 8k Divider is used for IN1_DIFF: DIRECT_DIV bit LOCK_8K bit 0 1 0 1 Used Divider Both bypassed (default) Lock 8k Divider DivN Divider Reserved 6 LOCK_8K 0 0 1 1 5-4 3-0 These bits select one of the four groups of leaky bucket configuration registers for IN1_DIFF: 00: Group 0; the addresses of the configuration registers are 31H ~ 34H. (default) BUCKET_SEL[1:0] 01: Group 1; the addresses of the configuration registers are 35H ~ 38H. 10: Group 2; the addresses of the configuration registers are 39H ~ 3CH. 11: Group 3; the addresses of the configuration registers are 3DH ~ 40H. These bits set the DPLL required frequency for IN1_DIFF: 0000: 8 kHz. 0001: 1.544 MHz (when the IN_SONET_SDH bit (b2, 09H) is `1') / 2.048 MHz (when the IN_SONET_SDH bit (b2, 09H) is `0'). 0010: 6.48 MHz. 0011: 19.44 MHz. (default) 0100: 25.92 MHz. IN_FREQ[3:0] 0101: 38.88 MHz. 0110 ~ 1000: Reserved. 1001: 2 kHz. 1010: 4 kHz. 1011 ~ 1111: Reserved. The required frequency should not be set higher than that of the input clock. Programming Information 65 June 19, 2006 IDT82V3255 WAN PLL IN2_DIFF_CNFG - Differential Input Clock 2 Configuration Address: 1AH Type: Read / Write Default Value: 00000011 7 DIRECT_DIV Bit 7 6 LOCK_8K Name DIRECT_DIV 5 BUCKET_SEL1 4 BUCKET_SEL0 3 IN_FREQ3 2 IN_FREQ2 1 IN_FREQ1 0 IN_FREQ0 Description Refer to the description of the LOCK_8K bit (b6, 1AH). This bit, together with the DIRECT_DIV bit (b7, 1AH), determines whether the DivN Divider or the Lock 8k Divider is used for IN2_DIFF: DIRECT_DIV bit LOCK_8K bit 0 1 0 1 Used Divider Both bypassed (default) Lock 8k Divider DivN Divider Reserved 6 LOCK_8K 0 0 1 1 5-4 3-0 These bits select one of the four groups of leaky bucket configuration registers for IN2_DIFF: 00: Group 0; the addresses of the configuration registers are 31H ~ 34H. (default) BUCKET_SEL[1:0] 01: Group 1; the addresses of the configuration registers are 35H ~ 38H. 10: Group 2; the addresses of the configuration registers are 39H ~ 3CH. 11: Group 3; the addresses of the configuration registers are 3DH ~ 40H. These bits set the DPLL required frequency for IN2_DIFF: 0000: 8 kHz. 0001: 1.544 MHz (when the IN_SONET_SDH bit (b2, 09H) is `1') / 2.048 MHz (when the IN_SONET_SDH bit (b2, 09H) is `0'). 0010: 6.48 MHz. 0011: 19.44 MHz. (default) 0100: 25.92 MHz. IN_FREQ[3:0] 0101: 38.88 MHz. 0110 ~ 1000: Reserved. 1001: 2 kHz. 1010: 4 kHz. 1011 ~ 1111: Reserved. For IN2_DIFF, the required frequency should not be set higher than that of the input clock. Programming Information 66 June 19, 2006 IDT82V3255 WAN PLL IN3_CMOS_CNFG - CMOS Input Clock 3 Configuration Address: 1DH Type: Read / Write Default Value: 00000011 7 DIRECT_DIV Bit 7 6 LOCK_8K Name DIRECT_DIV 5 BUCKET_SEL1 4 BUCKET_SEL0 3 IN_FREQ3 2 IN_FREQ2 1 IN_FREQ1 0 IN_FREQ0 Description Refer to the description of the LOCK_8K bit (b6, 1DH). This bit, together with the DIRECT_DIV bit (b7, 1DH), determines whether the DivN Divider or the Lock 8k Divider is used for IN3_CMOS: DIRECT_DIV bit LOCK_8K bit 0 1 0 1 Used Divider Both bypassed (default) Lock 8k Divider DivN Divider Reserved 6 LOCK_8K 0 0 1 1 5-4 3-0 These bits select one of the four groups of leaky bucket configuration registers for IN3_CMOS: 00: Group 0; the addresses of the configuration registers are 31H ~ 34H. (default) BUCKET_SEL[1:0] 01: Group 1; the addresses of the configuration registers are 35H ~ 38H. 10: Group 2; the addresses of the configuration registers are 39H ~ 3CH. 11: Group 3; the addresses of the configuration registers are 3DH ~ 40H. These bits set the DPLL required frequency for IN3_CMOS: 0000: 8 kHz. 0001: 1.544 MHz (when the IN_SONET_SDH bit (b2, 09H) is `1') / 2.048 MHz (when the IN_SONET_SDH bit (b2, 09H) is `0'). 0010: 6.48 MHz. 0011: 19.44 MHz. (default) 0100: 25.92 MHz. IN_FREQ[3:0] 0101: 38.88 MHz. 0110 ~ 1000: Reserved. 1001: 2 kHz. 1010: 4 kHz. 1011 ~ 1111: Reserved. For IN3_CMOS, the required frequency should not be set higher than that of the input clock. Programming Information 67 June 19, 2006 IDT82V3255 WAN PLL PRE_DIV_CH_CNFG - DivN Divider Channel Selection Address: 23H Type: Read / Write Default Value: XXXX0000 7 Bit 7-4 6 5 Name 4 3 PRE_DIV_CH_VALUE3 2 PRE_DIV_CH_VALUE2 1 PRE_DIV_CH_VALUE1 0 PRE_DIV_CH_VALUE0 Description 3-0 Reserved. This register is an indirect address register for Register 24H and 25H. These bits select an input clock. The value set in the PRE_DIVN_VALUE[14:0] bits (25H, 24H) is available for the selected input clock. 0000: Reserved. (default) 0001, 0010: Reserved. 0011: IN1_CMOS. PRE_DIV_CH_VALUE[3:0] 0100: IN2_CMOS. 0101: IN1_DIFF. 0110: IN2_DIFF. 0111, 1000: Reserved. 1001: IN3_CMOS. 1010 ~ 1111: Reserved. PRE_DIVN[7:0]_CNFG - DivN Divider Division Factor Configuration 1 Address: 24H Type: Read / Write Default Value: 00000000 7 PRE_DIVN_VA LUE7 Bit 7-0 6 PRE_DIVN_VA LUE6 Name 5 PRE_DIVN_VA LUE5 4 PRE_DIVN_VA LUE4 3 PRE_DIVN_VA LUE3 2 PRE_DIVN_VA LUE2 1 PRE_DIVN_VA LUE1 0 PRE_DIVN_VA LUE0 Description PRE_DIVN_VALUE[7:0] Refer to the description of the PRE_DIVN_VALUE[14:8] bits (b6~0, 25H). Programming Information 68 June 19, 2006 IDT82V3255 WAN PLL PRE_DIVN[14:8]_CNFG - DivN Divider Division Factor Configuration 2 Address: 25H Type: Read / Write Default Value: X0000000 7 Bit 7 6 PRE_DIVN_VAL UE14 Name 5 PRE_DIVN_VAL UE13 4 PRE_DIVN_VAL UE12 3 PRE_DIVN_VAL UE11 2 PRE_DIVN_VAL UE10 1 PRE_DIVN_VAL UE9 0 PRE_DIVN_VAL UE8 Description Reserved. If the value in the PRE_DIVN_VALUE[14:0] bits is plus 1, the division factor for an input clock will be gotten. The input clock is selected by the PRE_DIV_CH_VALUE[3:0] bits (b3~0, 23H). A value from `0' to `4BEF' (Hex) can be written into, corresponding to a division factor from 1 to 19440. The others are reserved. So the DivN Divider only supports an input clock whose frequency is lower than (<) 155.52 MHz. The division factor setting should observe the following order: 1. Write the lower eight bits of the division factor to the PRE_DIVN_VALUE[7:0] bits; 2. Write the higher eight bits of the division factor to the PRE_DIVN_VALUE[14:8] bits. 6-0 PRE_DIVN_VALUE[14:8] Programming Information 69 June 19, 2006 IDT82V3255 WAN PLL IN1_IN2_CMOS_SEL_PRIORITY_CNFG - CMOS Input Clock 1 & 2 Priority Configuration * Address: 27H Type: Read / Write Default Value: 00110010 7 IN2_CMOS_SE L_PRIORITY3 Bit 6 IN2_CMOS_SE L_PRIORITY2 Name 5 IN2_CMOS_SE L_PRIORITY1 4 IN2_CMOS_SE L_PRIORITY0 3 IN1_CMOS_SE L_PRIORITY3 2 IN1_CMOS_SE L_PRIORITY2 Description 1 IN1_CMOS_SE L_PRIORITY1 0 IN1_CMOS_SE L_PRIORITY0 7-4 3-0 These bits set the priority of the corresponding INn_CMOS. Here n is 2. 0000: Disable INn_CMOS for automatic selection. 0001: Priority 1. 0010: Priority 2. 0011: Priority 3. (default) 0100: Priority 4. 0101: Priority 5. 0110: Priority 6. INn_CMOS_SEL_PRIORITY[3:0] 0111: Priority 7. 1000: Priority 8. 1001: Priority 9. 1010: Priority 10. 1011: Priority 11. 1100: Priority 12. 1101: Priority 13. 1110: Priority 14. 1111: Priority 15. These bits set the priority of the corresponding INn_CMOS. Here n is 1. 0000: Disable INn_CMOS for automatic selection. 0001: Priority 1. 0010: Priority 2. (default) 0011: Priority 3. 0100: Priority 4. 0101: Priority 5. 0110: Priority 6. INn_CMOS_SEL_PRIORITY[3:0] 0111: Priority 7. 1000: Priority 8. 1001: Priority 9. 1010: Priority 10. 1011: Priority 11. 1100: Priority 12. 1101: Priority 13. 1110: Priority 14. 1111: Priority 15. Programming Information 70 June 19, 2006 IDT82V3255 WAN PLL IN1_IN2_DIFF_SEL_PRIORITY_CNFG - Differential Input Clock 1 & 2 Priority Configuration * Address: 28H Type: Read / Write Default Value: 00000000 7 IN2_DIFF_SEL_ PRIORITY3 Bit 6 IN2_DIFF_SEL_ PRIORITY2 Name 5 IN2_DIFF_SEL_ PRIORITY1 4 IN2_DIFF_SEL_ PRIORITY0 3 IN1_DIFF_SEL_ PRIORITY3 2 IN1_DIFF_SEL_ PRIORITY2 Description 1 IN1_DIFF_SEL_ PRIORITY1 0 IN1_DIFF_SEL_ PRIORITY0 7-4 3-0 These bits set the priority of the corresponding INn_DIFF. Here n is 2. 0000: Disable INn_DIFF for automatic selection. (default) 0001: Priority 1. 0010: Priority 2. 0011: Priority 3. 0100: Priority 4. 0101: Priority 5. 0110: Priority 6. INn_DIFF_SEL_PRIORITY[3:0] 0111: Priority 7. 1000: Priority 8. 1001: Priority 9. 1010: Priority 10. 1011: Priority 11. 1100: Priority 12. 1101: Priority 13. 1110: Priority 14. 1111: Priority 15. These bits set the priority of the corresponding INn_DIFF. Here n is 1. 0000: Disable INn_DIFF for automatic selection. (default) 0001: Priority 1. 0010: Priority 2. 0011: Priority 3. 0100: Priority 4. 0101: Priority 5. 0110: Priority 6. INn_DIFF_SEL_PRIORITY[3:0] 0111: Priority 7. 1000: Priority 8. 1001: Priority 9. 1010: Priority 10. 1011: Priority 11. 1100: Priority 12. 1101: Priority 13. 1110: Priority 14. 1111: Priority 15. Programming Information 71 June 19, 2006 IDT82V3255 WAN PLL IN3_CMOS_SEL_PRIORITY_CNFG - CMOS Input Clock 3 Priority Configuration * Address: 2AH Type: Read / Write Default Value: XXXX0100 7 Bit 7-4 6 Name 5 4 3 IN3_CMOS_SE L_PRIORITY3 2 IN3_CMOS_SE L_PRIORITY2 Description 1 IN3_CMOS_SE L_PRIORITY1 0 IN3_CMOS_SE L_PRIORITY0 3-0 Reserved. These bits set the priority of the corresponding IN3_CMOS. 0000: Disable INn for automatic selection. 0001: Priority 1. 0010: Priority 2. 0011: Priority 3. 0100: Priority 4. (default) 0101: Priority 5. 0110: Priority 6. IN3_CMOS_SEL_PRIORITY[3:0] 0111: Priority 7. 1000: Priority 8. 1001: Priority 9. 1010: Priority 10. 1011: Priority 11. 1100: Priority 12. 1101: Priority 13. 1110: Priority 14. 1111: Priority 15. Programming Information 72 June 19, 2006 IDT82V3255 WAN PLL 6.2.4 INPUT CLOCK QUALITY MONITORING CONFIGURATION & STATUS REGISTERS FREQ_MON_FACTOR_CNFG - Factor of Frequency Monitor Configuration Address: 2EH Type: Read / Write Default Value: XXXX1011 7 Bit 7-4 6 Name 5 4 3 FREQ_MON_F ACTOR3 2 FREQ_MON_F ACTOR2 1 FREQ_MON_F ACTOR1 0 FREQ_MON_F ACTOR0 Description 3-0 Reserved. These bits determine a factor. The factor has a relationship with the frequency hard alarm threshold in ppm (refer to the description of the ALL_FREQ_HARD_THRESHOLD[3:0] bits (b3~0, 2FH)) and with the frequency of the input clock with respect to the master clock in ppm (refer to the description of the IN_FREQ_VALUE[7:0] bits (b7~0, 42H)). The factor represents the accuracy of the frequency monitor and should be set according to the requirements of different applications. 0000: 0.0032. 0001: 0.0064. 0010: 0.0127. 0011: 0.0257. FREQ_MON_FACTOR[3:0] 0100: 0.0514. 0101: 0.103. 0110: 0.206. 0111: 0.412. 1000: 0.823. 1001: 1.646. 1010: 3.292. 1011: 3.81. (default) 1100 - 1111: 4.6. ALL_FREQ_MON_THRESHOLD_CNFG - Frequency Monitor Threshold for All Input Clocks Configuration Address: 2FH Type: Read / Write Default Value: XXXX0011 7 Bit 7-4 6 Name 5 4 3 ALL_FREQ_HARD_ THRESHOLD3 2 ALL_FREQ_HARD_ THRESHOLD2 1 ALL_FREQ_HARD_ THRESHOLD1 0 ALL_FREQ_HARD_ THRESHOLD0 Description 3-0 Reserved. These bits represent an unsigned integer. The frequency hard alarm threshold in ppm can be calculated as follows: ALL_FREQ_HARD_THRESHOLD[3:0] Frequency Hard Alarm Threshold (ppm) = (ALL_FREQ_HARD_THRESHOLD[3:0] + 1) X FREQ_MON_FACTOR[3:0] (b3~0, 2EH) This threshold is symmetrical about zero. Programming Information 73 June 19, 2006 IDT82V3255 WAN PLL UPPER_THRESHOLD_0_CNFG - Upper Threshold for Leaky Bucket Configuration 0 Address: 31H Type: Read / Write Default Value: 00000110 7 UPPER_THRE SHOLD_0_DAT A7 Bit 7-0 6 UPPER_THRE SHOLD_0_DAT A6 Name UPPER_THRESHOLD_0_DATA[7:0] 5 UPPER_THRE SHOLD_0_DAT A5 4 UPPER_THRE SHOLD_0_DAT A4 3 UPPER_THRE SHOLD_0_DAT A3 2 UPPER_THRE SHOLD_0_DAT A2 Description These bits set an upper threshold for the internal leaky bucket accumulator. When the number of the accumulated events is above this threshold, a no-activity alarm is raised. 1 UPPER_THRE SHOLD_0_DAT A1 0 UPPER_THRE SHOLD_0_DAT A0 LOWER_THRESHOLD_0_CNFG - Lower Threshold for Leaky Bucket Configuration 0 Address: 32H Type: Read / Write Default Value: 00000100 7 LOWER_THRE SHOLD_0_DAT A7 Bit 7-0 6 LOWER_THRE SHOLD_0_DAT A6 Name LOWER_THRESHOLD_0_DATA[7:0] 5 LOWER_THRE SHOLD_0_DAT A5 4 LOWER_THRE SHOLD_0_DAT A4 3 LOWER_THRE SHOLD_0_DAT A3 2 LOWER_THRE SHOLD_0_DAT A2 Description These bits set a lower threshold for the internal leaky bucket accumulator. When the number of the accumulated events is below this threshold, the no-activity alarm is cleared. 1 LOWER_THRE SHOLD_0_DAT A1 0 LOWER_THRE SHOLD_0_DAT A0 BUCKET_SIZE_0_CNFG - Bucket Size for Leaky Bucket Configuration 0 Address: 33H Type: Read / Write Default Value: 00001000 7 BUCKET_SIZE _0_DATA7 Bit 7-0 6 BUCKET_SIZE _0_DATA6 Name BUCKET_SIZE_0_DATA[7:0] 5 BUCKET_SIZE _0_DATA5 4 BUCKET_SIZE _0_DATA4 3 BUCKET_SIZE _0_DATA3 2 BUCKET_SIZE _0_DATA2 1 BUCKET_SIZE _0_DATA1 0 BUCKET_SIZE _0_DATA0 Description These bits set a bucket size for the internal leaky bucket accumulator. If the number of the accumulated events reach the bucket size, the accumulator will stop increasing even if further events are detected. Programming Information 74 June 19, 2006 IDT82V3255 WAN PLL DECAY_RATE_0_CNFG - Decay Rate for Leaky Bucket Configuration 0 Address: 34H Type: Read / Write Default Value: XXXXXX01 7 Bit 7-2 6 Name 5 4 3 2 Description 1 DECAY_RATE_ 0_DATA1 0 DECAY_RATE_ 0_DATA0 1-0 Reserved. These bits set a decay rate for the internal leaky bucket accumulator: 00: The accumulator decreases by 1 in every 128 ms with no event detected. DECAY_RATE_0_DATA[1:0] 01: The accumulator decreases by 1 in every 256 ms with no event detected. (default) 10: The accumulator decreases by 1 in every 512 ms with no event detected. 11: The accumulator decreases by 1 in every 1024 ms with no event detected. UPPER_THRESHOLD_1_CNFG - Upper Threshold for Leaky Bucket Configuration 1 Address: 35H Type: Read / Write Default Value: 00000110 7 UPPER_THRE SHOLD_1_DAT A7 Bit 7-0 6 UPPER_THRE SHOLD_1_DAT A6 Name UPPER_THRESHOLD_1_DATA[7:0] 5 UPPER_THRE SHOLD_1_DAT A5 4 UPPER_THRE SHOLD_1_DAT A4 3 UPPER_THRE SHOLD_1_DAT A3 2 UPPER_THRE SHOLD_1_DAT A2 Description These bits set an upper threshold for the internal leaky bucket accumulator. When the number of the accumulated events is above this threshold, a no-activity alarm is raised. 1 UPPER_THRE SHOLD_1_DAT A1 0 UPPER_THRE SHOLD_1_DAT A0 LOWER_THRESHOLD_1_CNFG - Lower Threshold for Leaky Bucket Configuration 1 Address: 36H Type: Read / Write Default Value: 00000100 7 LOWER_THRE SHOLD_1_DAT A7 Bit 7-0 6 LOWER_THRE SHOLD_1_DAT A6 Name 5 LOWER_THRE SHOLD_1_DAT A5 4 LOWER_THRE SHOLD_1_DAT A4 3 LOWER_THRE SHOLD_1_DAT A3 2 LOWER_THRE SHOLD_1_DAT A2 Description 1 LOWER_THRE SHOLD_1_DAT A1 0 LOWER_THRE SHOLD_1_DAT A0 These bits set a lower threshold for the internal leaky bucket accumulator. When the number of the accumulated LOWER_THRESHOLD_1_DATA[7:0] events is below this threshold, the no-activity alarm is cleared. Programming Information 75 June 19, 2006 IDT82V3255 WAN PLL BUCKET_SIZE_1_CNFG - Bucket Size for Leaky Bucket Configuration 1 Address: 37H Type: Read / Write Default Value: 00001000 7 BUCKET_SIZE _1_DATA7 Bit 7-0 6 BUCKET_SIZE _1_DATA6 Name 5 BUCKET_SIZE _1_DATA5 4 BUCKET_SIZE _1_DATA4 3 BUCKET_SIZE _1_DATA3 2 BUCKET_SIZE _1_DATA2 Description 1 BUCKET_SIZE _1_DATA1 0 BUCKET_SIZE _1_DATA0 These bits set a bucket size for the internal leaky bucket accumulator. If the number of the accumulated events reach BUCKET_SIZE_1_DATA[7:0] the bucket size, the accumulator will stop increasing even if further events are detected. DECAY_RATE_1_CNFG - Decay Rate for Leaky Bucket Configuration 1 Address: 38H Type: Read / Write Default Value: XXXXXX01 7 Bit 7-2 6 Name 5 4 3 2 Description 1 DECAY_RATE_ 1_DATA1 0 DECAY_RATE_ 1_DATA0 1-0 Reserved. These bits set a decay rate for the internal leaky bucket accumulator: 00: The accumulator decreases by 1 in every 128 ms with no event detected. DECAY_RATE_1_DATA[1:0] 01: The accumulator decreases by 1 in every 256 ms with no event detected. (default) 10: The accumulator decreases by 1 in every 512 ms with no event detected. 11: The accumulator decreases by 1 in every 1024 ms with no event detected. UPPER_THRESHOLD_2_CNFG - Upper Threshold for Leaky Bucket Configuration 2 Address: 39H Type: Read / Write Default Value: 00000110 7 UPPER_THRE SHOLD_2_DAT A7 Bit 7-0 6 UPPER_THRE SHOLD_2_DAT A6 Name 5 UPPER_THRE SHOLD_2_DAT A5 4 UPPER_THRE SHOLD_2_DAT A4 3 UPPER_THRE SHOLD_2_DAT A3 2 UPPER_THRE SHOLD_2_DAT A2 Description 1 UPPER_THRE SHOLD_2_DAT A1 0 UPPER_THRE SHOLD_2_DAT A0 These bits set an upper threshold for the internal leaky bucket accumulator. When the number of the accumuUPPER_THRESHOLD_2_DATA[7:0] lated events is above this threshold, a no-activity alarm is raised. Programming Information 76 June 19, 2006 IDT82V3255 WAN PLL LOWER_THRESHOLD_2_CNFG - Lower Threshold for Leaky Bucket Configuration 2 Address: 3AH Type: Read / Write Default Value: 00000100 7 LOWER_THRE SHOLD_2_DAT A7 Bit 7-0 6 LOWER_THRE SHOLD_2_DAT A6 Name LOWER_THRESHOLD_2_DATA[7:0] 5 LOWER_THRE SHOLD_2_DAT A5 4 LOWER_THRE SHOLD_2_DAT A4 3 LOWER_THRE SHOLD_2_DAT A3 2 LOWER_THRE SHOLD_2_DAT A2 Description These bits set a lower threshold for the internal leaky bucket accumulator. When the number of the accumulated events is below this threshold, the no-activity alarm is cleared. 1 LOWER_THRE SHOLD_2_DAT A1 0 LOWER_THRE SHOLD_2_DAT A0 BUCKET_SIZE_2_CNFG - Bucket Size for Leaky Bucket Configuration 2 Address: 3BH Type: Read / Write Default Value: 00001000 7 BUCKET_SIZE _2_DATA7 Bit 7-0 6 BUCKET_SIZE _2_DATA6 Name BUCKET_SIZE_2_DATA[7:0] 5 BUCKET_SIZE _2_DATA5 4 BUCKET_SIZE _2_DATA4 3 BUCKET_SIZE _2_DATA3 2 BUCKET_SIZE _2_DATA2 1 BUCKET_SIZE _2_DATA1 0 BUCKET_SIZE _2_DATA0 Description These bits set a bucket size for the internal leaky bucket accumulator. If the number of the accumulated events reach the bucket size, the accumulator will stop increasing even if further events are detected. DECAY_RATE_2_CNFG - Decay Rate for Leaky Bucket Configuration 2 Address: 3CH Type: Read / Write Default Value: XXXXXX01 7 Bit 7-2 6 Name 5 4 3 Description 2 1 DECAY_RATE_ 2_DATA1 0 DECAY_RATE_ 2_DATA0 1-0 Reserved. These bits set a decay rate for the internal leaky bucket accumulator: 00: The accumulator decreases by 1 in every 128 ms with no event detected. DECAY_RATE_2_DATA[1:0] 01: The accumulator decreases by 1 in every 256 ms with no event detected. (default) 10: The accumulator decreases by 1 in every 512 ms with no event detected. 11: The accumulator decreases by 1 in every 1024 ms with no event detected. Programming Information 77 June 19, 2006 IDT82V3255 WAN PLL UPPER_THRESHOLD_3_CNFG - Upper Threshold for Leaky Bucket Configuration 3 Address: 3DH Type: Read / Write Default Value: 00000110 7 UPPER_THRE SHOLD_3_DAT A7 Bit 7-0 6 UPPER_THRE SHOLD_3_DAT A6 Name UPPER_THRESHOLD_3_DATA[7:0] 5 UPPER_THRE SHOLD_3_DAT A5 4 UPPER_THRE SHOLD_3_DAT A4 3 UPPER_THRE SHOLD_3_DAT A3 2 UPPER_THRE SHOLD_3_DAT A2 Description These bits set an upper threshold for the internal leaky bucket accumulator. When the number of the accumulated events is above this threshold, a no-activity alarm is raised. 1 UPPER_THRE SHOLD_3_DAT A1 0 UPPER_THRE SHOLD_3_DAT A0 LOWER_THRESHOLD_3_CNFG - Lower Threshold for Leaky Bucket Configuration 3 Address: 3EH Type: Read / Write Default Value: 00000100 7 LOWER_THRE SHOLD_3_DAT A7 Bit 7-0 6 LOWER_THRE SHOLD_3_DAT A6 Name LOWER_THRESHOLD_3_DATA[7:0] 5 LOWER_THRE SHOLD_3_DAT A5 4 LOWER_THRE SHOLD_3_DAT A4 3 LOWER_THRE SHOLD_3_DAT A3 2 LOWER_THRE SHOLD_3_DAT A2 Description These bits set a lower threshold for the internal leaky bucket accumulator. When the number of the accumulated events is below this threshold, the no-activity alarm is cleared. 1 LOWER_THRE SHOLD_3_DAT A1 0 LOWER_THRE SHOLD_3_DAT A0 BUCKET_SIZE_3_CNFG - Bucket Size for Leaky Bucket Configuration 3 Address: 3FH Type: Read / Write Default Value: 00001000 7 BUCKET_SIZE _3_DATA7 Bit 7-0 6 BUCKET_SIZE _3_DATA6 Name BUCKET_SIZE_3_DATA[7:0] 5 BUCKET_SIZE _3_DATA5 4 BUCKET_SIZE _3_DATA4 3 BUCKET_SIZE _3_DATA3 2 BUCKET_SIZE _3_DATA2 1 BUCKET_SIZE _3_DATA1 0 BUCKET_SIZE _3_DATA0 Description These bits set a bucket size for the internal leaky bucket accumulator. If the number of the accumulated events reach the bucket size, the accumulator will stop increasing even if further events are detected. Programming Information 78 June 19, 2006 IDT82V3255 WAN PLL DECAY_RATE_3_CNFG - Decay Rate for Leaky Bucket Configuration 3 Address: 40H Type: Read / Write Default Value: XXXXXX01 7 Bit 7-2 6 Name 5 4 3 Description 2 1 DECAY_RATE_ 3_DATA1 0 DECAY_RATE_ 3_DATA0 1-0 Reserved. These bits set a decay rate for the internal leaky bucket accumulator: 00: The accumulator decreases by 1 in every 128 ms with no event detected. DECAY_RATE_3_DATA[1:0] 01: The accumulator decreases by 1 in every 256 ms with no event detected. (default) 10: The accumulator decreases by 1 in every 512 ms with no event detected. 11: The accumulator decreases by 1 in every 1024 ms with no event detected. IN_FREQ_READ_CH_CNFG - Input Clock Frequency Read Channel Selection Address: 41H Type: Read / Write Default Value: XXXX0000 7 Bit 7-4 6 Name 5 4 3 IN_FREQ_READ _CH3 2 IN_FREQ_READ _CH2 Description 1 IN_FREQ_READ _CH1 0 IN_FREQ_READ _CH0 3-0 Reserved. These bits select an input clock, the frequency of which with respect to the reference clock can be read. 0000: Reserved. (default) 0001, 0010: Reserved. 0011: IN1_CMOS. 0100: IN2_CMOS. IN_FREQ_READ_CH[3:0] 0101: IN1_DIFF. 0110: IN2_DIFF. 0111, 1000: Reserved. 1001: IN3_CMOS. 1010 ~ 1111: Reserved. Programming Information 79 June 19, 2006 IDT82V3255 WAN PLL IN_FREQ_READ_STS - Input Clock Frequency Read Value Address: 42H Type: Read Default Value: 00000000 7 IN_FREQ_VAL UE7 Bit 7-0 6 IN_FREQ_VAL UE6 Name 5 IN_FREQ_VAL UE5 4 IN_FREQ_VAL UE4 3 IN_FREQ_VAL UE3 2 IN_FREQ_VAL UE2 1 IN_FREQ_VAL UE1 0 IN_FREQ_VAL UE0 Description These bits represent a 2's complement signed integer. If the value is multiplied by the value in the FREQ_MON_FACTOR[3:0] bits (b3~0, 2EH), the frequency of an input clock with respect to the reference clock in ppm will IN_FREQ_VALUE[7:0] be gotten. The input clock is selected by the IN_FREQ_READ_CH[3:0] bits (b3~0, 41H). The value in these bits is updated every 16 seconds, starting when an input clock is selected. Programming Information 80 June 19, 2006 IDT82V3255 WAN PLL IN1_IN2_CMOS_STS - CMOS Input Clock 1 & 2 Status Address: 44H Type: Read Default Value: X110X110 7 6 IN2_CMOS_FRE Q_HARD_ALAR M Name IN2_CMOS_FREQ_HARD_ALARM 5 IN2_CMOS_NO_ ACTIVITY_ALAR M 4 IN2_CMOS_PH_ LOCK_ALARM 3 2 IN1_CMOS_FRE Q_HARD_ALAR M Description Reserved. This bit indicates whether IN2_CMOS is in frequency hard alarm status. 0: No frequency hard alarm. 1: In frequency hard alarm status. (default) This bit indicates whether IN2_CMOS is in no-activity alarm status. 0: No no-activity alarm. 1: In no-activity alarm status. (default) This bit indicates whether IN2_CMOS is in phase lock alarm status. 0: No phase lock alarm. (default) 1: In phase lock alarm status. If the PH_ALARM_TIMEOUT bit (b5, 09H) is `0', this bit is cleared by writing `1' to this bit; if the PH_ALARM_TIMEOUT bit (b5, 09H) is `1', this bit is cleared after a period (= TIME_OUT_VALUE[5:0] (b5~0, 08H) X MULTI_FACTOR[1:0] (b7~6, 08H) in second) which starts from when the alarm is raised. Reserved. This bit indicates whether IN1_CMOS is in frequency hard alarm status. 0: No frequency hard alarm. 1: In frequency hard alarm status. (default) This bit indicates whether IN1_CMOS is in no-activity alarm status. 0: No no-activity alarm. 1: In no-activity alarm status. (default) This bit indicates whether IN1_CMOS is in phase lock alarm status. 0: No phase lock alarm. (default) 1: In phase lock alarm status. If the PH_ALARM_TIMEOUT bit (b5, 09H) is `0', this bit is cleared by writing `1' to this bit; if the PH_ALARM_TIMEOUT bit (b5, 09H) is `1', this bit is cleared after a period (= TIME_OUT_VALUE[5:0] (b5~0, 08H) X MULTI_FACTOR[1:0] (b7~6, 08H) in second) which starts from when the alarm is raised. 1 IN1_CMOS_NO_ ACTIVITY_ALAR M 0 IN1_CMOS_PH_ LOCK_ALARM Bit 7 6 5 IN2_CMOS_NO_ACTIVITY_ALARM 4 IN2_CMOS_PH_LOCK_ALARM 3 2 IN1_CMOS_FREQ_HARD_ALARM 1 IN1_CMOS_NO_ACTIVITY_ALARM 0 IN1_CMOS_PH_LOCK_ALARM Programming Information 81 June 19, 2006 IDT82V3255 WAN PLL IN1_IN2_DIFF_STS - Differential Input Clock 1 & 2 Status Address: 45H Type: Read Default Value: X110X110 7 Bit 7 6 6 IN2_DIFF_FREQ _HARD_ALARM Name IN2_DIFF_FREQ_HARD_ALARM 5 IN2_DIFF_NO_A CTIVITY_ALARM 4 IN2_DIFF_PH_L OCK_ALARM 3 2 IN1_DIFF_FREQ _HARD_ALARM Description Reserved. This bit indicates whether IN2_DIFF is in frequency hard alarm status. 0: No frequency hard alarm. 1: In frequency hard alarm status. (default) This bit indicates whether IN2_DIFF is in no-activity alarm status. 0: No no-activity alarm. 1: In no-activity alarm status. (default) This bit indicates whether IN2_DIFF is in phase lock alarm status. 0: No phase lock alarm. (default) 1: In phase lock alarm status. If the PH_ALARM_TIMEOUT bit (b5, 09H) is `0', this bit is cleared by writing `1' to this bit; if the PH_ALARM_TIMEOUT bit (b5, 09H) is `1', this bit is cleared after a period (= TIME_OUT_VALUE[5:0] (b5~0, 08H) X MULTI_FACTOR[1:0] (b7~6, 08H) in second) which starts from when the alarm is raised. Reserved. This bit indicates whether IN1_DIFF is in frequency hard alarm status. 0: No frequency hard alarm. 1: In frequency hard alarm status. (default) This bit indicates whether IN1_DIFF is in no-activity alarm status. 0: No no-activity alarm. 1: In no-activity alarm status. (default) This bit indicates whether IN1_DIFF is in phase lock alarm status. 0: No phase lock alarm. (default) 1: In phase lock alarm status. If the PH_ALARM_TIMEOUT bit (b5, 09H) is `0', this bit is cleared by writing `1' to this bit; if the PH_ALARM_TIMEOUT bit (b5, 09H) is `1', this bit is cleared after a period (= TIME_OUT_VALUE[5:0] (b5~0, 08H) X MULTI_FACTOR[1:0] (b7~6, 08H) in second) which starts from when the alarm is raised. 1 IN1_DIFF_NO_A CTIVITY_ALARM 0 IN1_DIFF_PH_L OCK_ALARM 5 IN2_DIFF_NO_ACTIVITY_ALARM 4 IN2_DIFF_PH_LOCK_ALARM 3 2 IN1_DIFF_FREQ_HARD_ALARM 1 IN1_DIFF_NO_ACTIVITY_ALARM 0 IN1_DIFF_PH_LOCK_ALARM Programming Information 82 June 19, 2006 IDT82V3255 WAN PLL IN3_CMOS_STS - CMOS Input Clock 3 Status Address: 47H Type: Read Default Value: XXXXX110 7 6 5 4 3 2 IN3_CMOS_FRE Q_HARD_ALAR M Description 1 IN3_CMOS_NO_ ACTIVITY_ALAR M 0 IN3_CMOS_PH_ LOCK_ALARM Bit 7-3 2 Name - 1 0 Reserved. This bit indicates whether IN3_CMOS is in frequency hard alarm status. IN3_CMOS_FREQ_HARD_ALARM 0: No frequency hard alarm. 1: In frequency hard alarm status. (default) This bit indicates whether IN3_CMOS is in no-activity alarm status. IN3_CMOS_NO_ACTIVITY_ALARM 0: No no-activity alarm. 1: In no-activity alarm status. (default) This bit indicates whether IN3_CMOS is in phase lock alarm status. 0: No phase lock alarm. (default) 1: In phase lock alarm status. IN3_CMOS_PH_LOCK_ALARM If the PH_ALARM_TIMEOUT bit (b5, 09H) is `0', this bit is cleared by writing `1' to this bit; if the PH_ALARM_TIMEOUT bit (b5, 09H) is `1', this bit is cleared after a period (= TIME_OUT_VALUE[5:0] (b5~0, 08H) X MULTI_FACTOR[1:0] (b7~6, 08H) in second) which starts from when the alarm is raised. Programming Information 83 June 19, 2006 IDT82V3255 WAN PLL 6.2.5 T0 / T4 DPLL INPUT CLOCK SELECTION REGISTERS INPUT_VALID1_STS - Input Clocks Validity 1 Address: 4AH Type: Read Default Value: XX0000XX 7 Bit 7-6 5-4 Name INn_DIFF 6 5 IN2_DIFF 4 IN1_DIFF 3 IN2_CMOS 2 IN1_CMOS 1 0 - Description Reserved. This bit indicates the validity of the corresponding INn_DIFF. Here n is 2 or 1. 0: Invalid. (default) 1: Valid. This bit indicates the validity of the corresponding INn_CMOS. Here n is 2 or 1. 0: Invalid. (default) 1: Valid. Reserved. 3-2 1-0 INn_CMOS - INPUT_VALID2_STS - Input Clocks Validity 2 Address: 4BH Type: Read Default Value: XXXXXXX0 7 Bit 7-1 0 Name IN3_CMOS 6 5 4 3 Description Reserved. This bit indicates the validity of the corresponding IN3_CMOS. 0: Invalid. (default) 1: Valid. 2 1 0 IN3_CMOS Programming Information 84 June 19, 2006 IDT82V3255 WAN PLL PRIORITY_TABLE1_STS - Priority Status 1 * Address: 4EH Type: Read Default Value: 00000000 7 HIGHEST_PRI ORITY_VALIDA TED3 Bit 6 HIGHEST_PRI ORITY_VALIDA TED2 Name 5 HIGHEST_PRI ORITY_VALIDA TED1 4 HIGHEST_PRI ORITY_VALIDA TED0 3 CURRENTLY_S ELECTED_INP UT3 2 CURRENTLY_S ELECTED_INP UT2 Description 1 CURRENTLY_S ELECTED_INP UT1 0 CURRENTLY_S ELECTED_INP UT0 7-4 3-0 These bits indicate a qualified input clock with the highest priority. 0000: No input clock is qualified. (default) 0001, 0010: Reserved. 0011: IN1_CMOS. 0100: IN2_CMOS. HIGHEST_PRIORITY_VALIDATED[3:0] 0101: IN1_DIFF. 0110: IN2_DIFF. 0111, 1000: Reserved. 1001: IN3_CMOS. 1010 ~ 1111: Reserved. These bits indicate the T0/T4 selected input clock. 0000: No input clock is selected; or the T4 selected input clock is the T0 DPLL output. (default) 0001, 0010: Reserved. 0011: IN1_CMOS is selected. 0100: IN2_CMOS is selected. CURRENTLY_SELECTED_INPUT[3:0] 0101: IN1_DIFF is selected. 0110: IN2_DIFF is selected. 0111, 1000: Reserved. 1001: IN3_CMOS is selected. 1010 ~ 1111: Reserved. Programming Information 85 June 19, 2006 IDT82V3255 WAN PLL PRIORITY_TABLE2_STS - Priority Status 2 * Address: 4FH Type: Read Default Value: 00000000 7 THIRD_HIGHE ST_PRIORITY_ VALIDATED3 Bit 6 THIRD_HIGHE ST_PRIORITY_ VALIDATED2 5 THIRD_HIGHE ST_PRIORITY_ VALIDATED1 Name 4 THIRD_HIGHE ST_PRIORITY_ VALIDATED0 3 SECOND_HIGH EST_PRIORITY _VALIDATED3 2 SECOND_HIGH EST_PRIORITY _VALIDATED2 Description 1 SECOND_HIGH EST_PRIORITY _VALIDATED1 0 SECOND_HIGH EST_PRIORITY _VALIDATED0 7-4 3-0 These bits indicate a qualified input clock with the third highest priority. 0000: No input clock is qualified. (default) 0001, 0010: Reserved. 0011: IN1_CMOS. 0100: IN2_CMOS. THIRD_HIGHEST_PRIORITY_VALIDATED[3:0] 0101: IN1_DIFF. 0110: IN2_DIFF. 0111, 1000: Reserved. 1001: IN3_CMOS. 1010 ~ 1111: Reserved. These bits indicate a qualified input clock with the second highest priority. 0000: No input clock is qualified. (default) 0001, 0010: Reserved. 0011: IN1_CMOS. 0100: IN2_CMOS. SECOND_HIGHEST_PRIORITY_VALIDATED[3:0] 0101: IN1_DIFF. 0110: IN2_DIFF. 0111, 1000: Reserved. 1001: IN3_CMOS. 1010 ~ 1111: Reserved. T0_INPUT_SEL_CNFG - T0 Selected Input Clock Configuration Address: 50H Type: Read / Write Default Value: XXXX0000 7 Bit 7-4 6 Name 5 4 3 T0_INPUT_SEL3 2 T0_INPUT_SEL2 1 T0_INPUT_SEL1 0 T0_INPUT_SEL0 Description 3-0 Reserved. This bit determines T0 input clock selection. It is valid only when the EXT_SW bit (b4, 0BH) is `0'. 0000: Automatic selection. (default) 0001, 0010: Reserved. 0011: Forced selection - IN1_CMOS is selected. 0100: Forced selection - IN2_CMOS is selected. T0_INPUT_SEL[3:0] 0101: Forced selection - IN1_DIFF is selected. 0110: Forced selection - IN2_DIFF is selected. 0111, 1000: Reserved. 1001: Forced selection - IN3_CMOS is selected. 1010 ~ 1111: Reserved. Programming Information 86 June 19, 2006 IDT82V3255 WAN PLL T4_INPUT_SEL_CNFG - T4 Selected Input Clock Configuration Address: 51H Type: Read / Write Default Value: X0000000 7 Bit 7 6 6 T4_LOCK_T0 Name 5 T0_FOR_T4 4 T4_TEST_T0_PH 3 T4_INPUT_SEL3 2 T4_INPUT_SEL2 1 T4_INPUT_SEL1 0 T4_INPUT_SEL0 Description 5 4 3-0 Reserved. This bit determines whether the T4 DPLL locks to a T0 DPLL output or locks independently from the T0 DPLL. T4_LOCK_T0 0: Independently from the T0 path. (default) 1: Locks to a 77.76 MHz or 8 kHz signal from the T0 DPLL 77.76 MHz path. This bit is valid only when the T4_LOCK_T0 bit (b6, 51H) is `1'. It determines whether a 77.76 MHz or 8 kHz signal from the T0 DPLL 77.76 MHz path is selected by the T4 DPLL. T0_FOR_T4 0: 77.76 MHz. (default) 1: 8 kHz. This bit determines whether T4 selected input clock is compared with the feedback signal of the T4 DPLL for T4 DPLL locking or is compared with the T0 selected input clock to get the phase difference between T0 and T4 selected input clocks. T4_TEST_T0_PH 0: The T4 DPLL output. (default) 1: The T0 selected input clock. These bits are valid only when the T4_LOCK_T0 bit (b6, 51H) is `0'. They determines the T4 DPLL input clock selection. 0000: Automatic selection. (default) 0001, 0010: Reserved. 0011: Forced selection - IN1_CMOS is selected. 0100: Forced selection - IN2_CMOS is selected. T4_INPUT_SEL[3:0] 0101: Forced selection - IN1_DIFF is selected. 0110: Forced selection - IN2_DIFF is selected. 0111, 1000: Reserved. 1001: Forced selection - IN3_CMOS is selected. 1010 ~ 1111: Reserved. Programming Information 87 June 19, 2006 IDT82V3255 WAN PLL 6.2.6 T0 / T4 DPLL STATE MACHINE CONTROL REGISTERS OPERATING_STS - DPLL Operating Status Address: 52H Type: Read Default Value: 10000001 7 EX_SYNC_ALA RM_MON Bit 7 6 T4_DPLL_LO CK Name EX_SYNC_ALARM_MON 5 T0_DPLL_SOFT _FREQ_ALARM 4 T4_DPLL_SOFT _FREQ_ALARM 3 T0_DPLL_LO CK 2 T0_DPLL_OPER ATING_MODE2 Description 1 T0_DPLL_OPER ATING_MODE1 0 T0_DPLL_OPER ATING_MODE0 6 5 4 3 2-0 This bit indicates whether the selected frame sync input signal is in external sync alarm status. 0: No external sync alarm. 1: In external sync alarm status. (default) This bit indicates the T4 DPLL locking status. T4_DPLL_LOCK 0: Unlocked. (default) 1: Locked. This bit indicates whether the T0 DPLL is in soft alarm status. T0_DPLL_SOFT_FREQ_ALARM 0: No T0 DPLL soft alarm. (default) 1: In T0 DPLL soft alarm status. This bit indicates whether the T4 DPLL is in soft alarm status. T4_DPLL_SOFT_FREQ_ALARM 0: No T4 DPLL soft alarm. (default) 1: In T4 DPLL soft alarm status. This bit indicates the T0 DPLL locking status. T0_DPLL_LOCK 0: Unlocked. (default) 1: Locked. These bits indicate the current operating mode of T0 DPLL. 000: Reserved. 001: Free-Run. (default) 010: Holdover. T0_DPLL_OPERATING_MODE[2:0] 011: Reserved. 100: Locked. 101: Pre-Locked2. 110: Pre-Locked. 111: Lost-Phase. Programming Information 88 June 19, 2006 IDT82V3255 WAN PLL T0_OPERATING_MODE_CNFG - T0 DPLL Operating Mode Configuration Address: 53H Type: Read / Write Default Value: XXXXX000 7 Bit 7-3 6 Name Reserved. These bits control the T0 DPLL operating mode. 000: Automatic. (default) 001: Forced - Free-Run. 010: Forced - Holdover. T0_OPERATING_MODE[2:0] 011: Reserved. 100: Forced - Locked. 101: Forced - Pre-Locked2. 110: Forced - Pre-Locked. 111: Forced - Lost-Phase. 5 4 3 2 T0_OPERATING_MODE2 1 T0_OPERATING_MODE1 Description 0 T0_OPERATING_MODE0 2-0 T4_OPERATING_MODE_CNFG - T4 DPLL Operating Mode Configuration Address: 54H Type: Read / Write Default Value: XXXXX000 7 Bit 7-3 6 Name Reserved. These bits control the T4 DPLL operating mode. 000: Automatic. (default) 001: Forced - Free-Run. T4_OPERATING_MODE[2:0] 010: Forced - Holdover. 011: Reserved. 100: Forced - Locked. 101, 110, 111: Reserved. 5 4 3 2 T4_OPERATING_MODE2 1 T4_OPERATING_MODE1 Description 0 T4_OPERATING_MODE0 2-0 Programming Information 89 June 19, 2006 IDT82V3255 WAN PLL 6.2.7 T0 / T4 DPLL & APLL CONFIGURATION REGISTERS T0_DPLL_APLL_PATH_CNFG - T0 DPLL & APLL Path Configuration Address: 55H Type: Read / Write Default Value: 00000X0X 7 T0_APLL_PATH 3 Bit 6 T0_APLL_PA TH2 Name 5 T0_APLL_PA TH1 4 T0_APLL_PA TH0 3 T0_GSM_OBSAI_ 16E1_16T1_SEL1 2 T0_GSM_OBSAI_ 16E1_16T1_SEL0 Description 1 T0_12E1_24T1_ E3_T3_SEL1 0 T0_12E1_24T1_ E3_T3_SEL0 7-4 3-2 1-0 These bits select an input to the T0 APLL. 0000: The output of T0 DPLL 77.76 MHz path. (default) 0001: The output of T0 DPLL 12E1/24T1/E3/T3 path. 0010: The output of T0 DPLL 16E1/16T1 path. 0011: The output of T0 DPLL GSM/OBSAI/16E1/16T1 path. T0_APLL_PATH[3:0] 0100: The output of T4 DPLL 77.76 MHz path. 0101: The output of T4 DPLL 12E1/24T1/E3/T3 path. 0110: The output of T4 DPLL 16E1/16T1 path. 0111: The output of T4 DPLL GSM/GPS/16E1/16T1 path. 1XXX: Reserved. These bits select an output clock from the T0 DPLL GSM/OBSAI/16E1/16T1 path. 00: 16E1. 01: 16T1. T0_GSM_OBSAI_16E1_16T1_SEL[1:0] 10: GSM. 11: OBSAI. The default value of the T0_GSM_OBSAI_16E1_16T1_SEL0 bit is determined by the SONET/SDH pin during reset. These bits select an output clock from the T0 DPLL 12E1/24T1/E3/T3 path. 00: 12E1. 01: 24T1. T0_12E1_24T1_E3_T3_SEL[1:0] 10: E3. 11: T3. The default value of the T0_12E1_24T1_E3_T3_SEL0 bit is determined by the SONET/SDH pin during reset. Programming Information 90 June 19, 2006 IDT82V3255 WAN PLL T0_DPLL_START_BW_DAMPING_CNFG - T0 DPLL Start Bandwidth & Damping Factor Configuration Address: 56H Type: Read / Write Default Value: 01101111 7 T0_DPLL_STA RT_DAMPING2 Bit 6 T0_DPLL_STA RT_DAMPING1 Name 5 T0_DPLL_STA RT_DAMPING0 4 T0_DPLL_STA RT_BW4 3 T0_DPLL_STA RT_BW3 2 T0_DPLL_STA RT_BW2 Description 1 T0_DPLL_STA RT_BW1 0 T0_DPLL_STA RT_BW0 7-5 4-0 These bits set the starting damping factor for T0 DPLL. 000: Reserved. 001: 1.2. 010: 2.5. T0_DPLL_START_DAMPING[2:0] 011: 5. (default) 100: 10. 101: 20. 110, 111: Reserved. These bits set the starting bandwidth for T0 DPLL. 00XXX: Reserved. 01000: 0.1 Hz. 01001: 0.3 Hz. 01010: 0.6 Hz. 01011: 1.2 Hz. 01100: 2.5 Hz. T0_DPLL_START_BW[4:0] 01101: 4 Hz. 01110: 8 Hz. 01111: 18 Hz. (default) 10000: 35 Hz. 10001: 70 Hz. 10010: 560 Hz. 10011 ~ 11111: Reserved. Programming Information 91 June 19, 2006 IDT82V3255 WAN PLL T0_DPLL_ACQ_BW_DAMPING_CNFG - T0 DPLL Acquisition Bandwidth & Damping Factor Configuration Address: 57H Type: Read / Write Default Value: 01101111 7 T0_DPLL_ACQ _DAMPING2 Bit 6 T0_DPLL_ACQ _DAMPING1 Name 5 T0_DPLL_ACQ _DAMPING0 4 T0_DPLL_ACQ _BW4 3 T0_DPLL_ACQ _BW3 2 T0_DPLL_ACQ _BW2 Description 1 T0_DPLL_ACQ _BW1 0 T0_DPLL_ACQ _BW0 7-5 4-0 These bits set the acquisition damping factor for T0 DPLL. 000: Reserved. 001: 1.2. 010: 2.5. T0_DPLL_ACQ_DAMPING[2:0] 011: 5. (default) 100: 10. 101: 20. 110, 111: Reserved. These bits set the acquisition bandwidth for T0 DPLL. 00XXX: Reserved. 01000: 0.1 Hz. 01001: 0.3 Hz. 01010: 0.6 Hz. 01011: 1.2 Hz. 01100: 2.5 Hz. T0_DPLL_ACQ_BW[4:0] 01101: 4 Hz. 01110: 8 Hz. 01111: 18 Hz. (default) 10000: 35 Hz. 10001: 70 Hz. 10010: 560 Hz. 10011 ~ 11111: Reserved. Programming Information 92 June 19, 2006 IDT82V3255 WAN PLL T0_DPLL_LOCKED_BW_DAMPING_CNFG - T0 DPLL Locked Bandwidth & Damping Factor Configuration Address: 58H Type: Read / Write Default Value: 01101111 7 T0_DPLL_LOCK ED_DAMPING2 Bit 6 T0_DPLL_LOCK ED_DAMPING1 Name 5 T0_DPLL_LOCK ED_DAMPING0 4 T0_DPLL_LOC KED_BW4 3 T0_DPLL_LOC KED_BW3 2 T0_DPLL_LOC KED_BW2 Description 1 T0_DPLL_LOC KED_BW1 0 T0_DPLL_LOC KED_BW0 7-5 4-0 These bits set the locked damping factor for T0 DPLL. 000: Reserved. 001: 1.2. 010: 2.5. T0_DPLL_LOCKED_DAMPING[2:0] 011: 5. (default) 100: 10. 101: 20. 110, 111: Reserved. These bits set the locked bandwidth for T0 DPLL. 00XXX: Reserved. 01000: 0.1 Hz. 01001: 0.3 Hz. 01010: 0.6 Hz. 01011: 1.2 Hz. (default) 01100: 2.5 Hz. T0_DPLL_LOCKED_BW[4:0] 01101: 4 Hz. 01110: 8 Hz. 01111: 18 Hz. 10000: 35 Hz. 10001: 70 Hz. 10010: 560 Hz. 10011 ~ 11111: Reserved. T0_BW_OVERSHOOT_CNFG - T0 DPLL Bandwidth Overshoot Configuration Address: 59H Type: Read / Write Default Value: 1XXX1XXX 7 AUTO_BW_SEL Bit Name 6 5 4 3 T0_LIMT Description 2 1 0 - 7 6-4 3 2-0 This bit determines whether starting or acquisition bandwidth / damping factor is used for T0 DPLL. 0: The starting and acquisition bandwidths / damping factors are not used. Only the locked bandwidth / damping factor is used AUTO_BW_SEL regardless of the T0 DPLL locking stage. 1: The starting, acquisition or locked bandwidth / damping factor is used automatically depending on different T0 DPLL locking stages. (default) Reserved. This bit determines whether the integral path value is frozen when the T0 DPLL hard limit is reached. T0_LIMT 0: Not frozen. 1: Frozen. It will minimize the subsequent overshoot when T0 DPLL is pulling in. (default) Reserved. Programming Information 93 June 19, 2006 IDT82V3255 WAN PLL PHASE_LOSS_COARSE_LIMIT_CNFG - Phase Loss Coarse Detector Limit Configuration * Address: 5AH Type: Read / Write Default Value: 10000101 7 COARSE_PH_L OS_LIMT_EN Bit 7 6 Name 6 WIDE_EN 5 MULTI_PH_APP 4 MULTI_PH_8K_ 4K_2K_EN 3 PH_LOS_COA RSE_LIMT3 2 PH_LOS_COA RSE_LIMT2 1 PH_LOS_COA RSE_LIMT1 0 PH_LOS_COA RSE_LIMT0 Description 5 This bit controls whether the occurrence of the coarse phase loss will result in the T0/T4 DPLL unlocked. COARSE_PH_LOS_LIMT_EN 0: Disabled. 1: Enabled. (default) WIDE_EN Refer to the description of the MULTI_PH_8K_4K_2K_EN bit (b4, 5AH). This bit determines whether the PFD output of T0/T4 DPLL is limited to 1 UI or is limited to the coarse phase limit. 0: Limited to 1 UI. (default) 1: Limited to the coarse phase limit. When the selected input clock is of 2 kHz, 4 kHz or 8 kHz, the coarse phase limit depends MULTI_PH_APP on the MULTI_PH_8K_4K_2K_EN bit, the WIDE_EN bit and the PH_LOS_COARSE_LIMT[3:0] bits; when the selected input clock is of other frequencies but 2 kHz, 4 kHz and 8 kHz, the coarse phase limit depends on the WIDE_EN bit and the PH_LOS_COARSE_LIMT[3:0] bits. Refer to the description of the MULTI_PH_8K_4K_2K_EN bit (b4, 5AH) for details. This bit, together with the WIDE_EN bit (b6, 5AH) and the PH_LOS_COARSE_LIMT[3:0] bits (b3~0, 5AH), determines the coarse phase limit when the selected input clock is of 2 kHz, 4 kHz or 8 kHz. When the selected input clock is of other frequencies but 2 kHz, 4 kHz and 8 kHz, the coarse phase limit depends on the WIDE_EN bit and the PH_LOS_COARSE_LIMT[3:0] bits. Selected Input Clock MULTI_PH_8K_4K_2K_EN WIDE_EN Coarse Phase Limit 1 UI 1 UI set by the PH_LOS_COARSE_LIMT[3:0] bits (b3~0, 5AH). 1 UI set by the PH_LOS_COARSE_LIMT[3:0] bits (b3~0, 5AH). 4 MULTI_PH_8K_4K_2K_EN 2 kHz, 4 kHz or 8 kHz 0 1 don't-care 0 1 0 other than 2 kHz, 4 kHz and 8 kHz don't-care 1 These bit set the coarse phase limit. The limit is used only in some cases. Refer to the description of the MULTI_PH_8K_4K_2K_EN bit (b4, 5AH). 0000: 1 UI. 0001: 3 UI. 0010: 7 UI. 0011: 15 UI. 3 - 0 PH_LOS_COARSE_LIMT[3:0] 0100: 31 UI. 0101: 63 UI. (default) 0110: 127 UI. 0111: 255 UI. 1000: 511 UI. 1001: 1023 UI (T0); Reserved (T4). 1010-1111: Reserved. Programming Information 94 June 19, 2006 IDT82V3255 WAN PLL PHASE_LOSS_FINE_LIMIT_CNFG - Phase Loss Fine Detector Limit Configuration * Address: 5BH Type: Read / Write Default Value: 10XXX010 7 FINE_PH_LOS_ LIMT_EN Bit 7 6 FAST_LOS_SW Name 5 4 3 2 PH_LOS_FINE _LIMT2 Description 1 PH_LOS_FINE _LIMT1 0 PH_LOS_FINE _LIMT0 6 5-3 2-0 This bit controls whether the occurrence of the fine phase loss will result in the T0/T4 DPLL unlocked. FINE_PH_LOS_LIMT_EN 0: Disabled. 1: Enabled. (default) The value in this bit can be switched only when it is available for T0 path; this bit is always `1' when it is available for T4 path. This bit controls whether the occurrence of the fast loss will result in the T0/T4 DPLL unlocked. FAST_LOS_SW 0: Does not result in the T0 DPLL unlocked. T0 DPLL will enter Temp-Holdover mode automatically. (default) 1: Results in the T0/T4 DPLL unlocked. For T0 path, T0 DPLL will enter Lost-Phase mode if the T0 DPLL operating mode is switched automatically. Reserved. These bits set a fine phase limit. 000: 0. 001: (45 ~ 90 ). 010: (90 ~ 180 ). (default) PH_LOS_FINE_LIMT[2:0] 011: (180 ~ 360 ). 100: (20 ns ~ 25 ns). 101: (60 ns ~ 65 ns). 110: (120 ns ~ 125 ns). 111: (950 ns ~ 955 ns). Programming Information 95 June 19, 2006 IDT82V3255 WAN PLL T0_HOLDOVER_MODE_CNFG - T0 DPLL Holdover Mode Configuration Address: 5CH Type: Read / Write Default Value: 010001XX 7 MAN_HOLDOV ER Bit 7 6 6 AUTO_AVG Name MAN_HOLDOVER AUTO_AVG 5 FAST_AVG 4 READ_AVG 3 TEMP_HOLDO VER_MODE1 2 TEMP_HOLDO VER_MODE0 Description Refer to the description of the FAST_AVG bit (b5, 5CH). Refer to the description of the FAST_AVG bit (b5, 5CH). This bit, together with the AUTO_AVG bit (b6, 5CH) and the MAN_HOLDOVER bit (b7, 5CH), determines a frequency offset acquiring method in T0 DPLL Holdover Mode. MAN_HOLDOVER 5 FAST_AVG 0 1 AUTO_AVG 0 1 don't-care FAST_AVG don't-care 0 1 Frequency Offset Acquiring Method Automatic Instantaneous Automatic Slow Averaged (default) Automatic Fast Averaged Manual 1 0 - 4 3-2 1-0 This bit controls the holdover frequency offset reading, which is read from the T0_HOLDOVER_FREQ[23:0] bits (5FH ~ 5DH). 0: The value read from the T0_HOLDOVER_FREQ[23:0] bits (5FH ~ 5DH) is equal to the one written to them. READ_AVG (default) 1: The value read from the T0_HOLDOVER_FREQ[23:0] bits (5FH ~ 5DH) is not equal to the one written to them. The value is acquired by Automatic Slow Averaged method if the FAST_AVG bit (b5, 5CH) is `0'; or is acquired by Automatic Fast Averaged method if the FAST_AVG bit (b5, 5CH) is `1'. These bits determine the frequency offset acquiring method in T0 DPLL Temp-Holdover Mode. 00: The method is the same as that used in T0 DPLL Holdover mode. TEMP_HOLDOVER_MODE[1:0] 01: Automatic Instantaneous. (default) 10: Automatic Fast Averaged. 11: Automatic Slow Averaged. Reserved. T0_HOLDOVER_FREQ[7:0]_CNFG - T0 DPLL Holdover Frequency Configuration 1 Address: 5DH Type: Read / Write Default Value: 00000000 7 T0_HOLDOVER _FREQ7 Bit 7-0 6 T0_HOLDOVER _FREQ6 Name 5 T0_HOLDOVER _FREQ5 4 T0_HOLDOVE R_FREQ4 3 T0_HOLDOVE R_FREQ3 2 T0_HOLDOVE R_FREQ2 1 T0_HOLDOVE R_FREQ1 0 T0_HOLDOVE R_FREQ0 Description T0_HOLDOVER_FREQ[7:0] Refer to the description of the T0_HOLDOVER_FREQ[23:16] bits (b7~0, 5FH). Programming Information 96 June 19, 2006 IDT82V3255 WAN PLL T0_HOLDOVER_FREQ[15:8]_CNFG - T0 DPLL Holdover Frequency Configuration 2 Address: 5EH Type: Read / Write Default Value: 00000000 7 T0_HOLDOVER _FREQ15 Bit 7-0 6 T0_HOLDOVER _FREQ14 Name 5 T0_HOLDOVER _FREQ13 4 T0_HOLDOVE R_FREQ12 3 T0_HOLDOVE R_FREQ11 2 T0_HOLDOVE R_FREQ10 Description 1 T0_HOLDOVE R_FREQ9 0 T0_HOLDOVE R_FREQ8 T0_HOLDOVER_FREQ[15:8] Refer to the description of the T0_HOLDOVER_FREQ[23:16] bits (b7~0, 5FH). T0_HOLDOVER_FREQ[23:16]_CNFG - T0 DPLL Holdover Frequency Configuration 3 Address: 5FH Type: Read / Write Default Value: 00000000 7 T0_HOLDOVER _FREQ23 Bit 7-0 6 T0_HOLDOVER _FREQ22 Name 5 T0_HOLDOVER _FREQ21 4 T0_HOLDOVE R_FREQ20 3 T0_HOLDOVE R_FREQ19 2 T0_HOLDOVE R_FREQ18 Description 1 T0_HOLDOVE R_FREQ17 0 T0_HOLDOVE R_FREQ16 The T0_HOLDOVER_FREQ[23:0] bits represent a 2's complement signed integer. In T0 DPLL Holdover mode, the value written to these bits multiplied by 0.000011 is the frequency offset set manuT0_HOLDOVER_FREQ[23:16] ally; the value read from these bits multiplied by 0.000011 is the frequency offset automatically slow or fast averaged or manually set, as determined by the READ_AVG bit (b4, 5CH) and the FAST_AVG bit (b5, 5CH). Programming Information 97 June 19, 2006 IDT82V3255 WAN PLL T4_DPLL_APLL_PATH_CNFG - T4 DPLL & APLL Path Configuration Address: 60H Type: Read / Write Default Value: 01000X0X 7 T4_APLL_PATH 3 Bit 6 T4_APLL_PA TH2 Name 5 T4_APLL_PA TH1 4 T4_APLL_PA TH0 3 T4_GSM_GPS_16 E1_16T1_SEL1 2 T4_GSM_GPS_16 E1_16T1_SEL0 Description 1 T4_12E1_24T1_ E3_T3_SEL1 0 T4_12E1_24T1_ E3_T3_SEL0 7-4 3-2 1-0 These bits select an input to the T4 APLL. 0000: The output of T0 DPLL 77.76 MHz path. 0001: The output of T0 DPLL 12E1/24T1/E3/T3 path. 0010: The output of T0 DPLL 16E1/16T1 path. 0011: The output of T0 DPLL GSM/OBSAI/16E1/16T1 path. T4_APLL_PATH[3:0] 0100: The output of T4 DPLL 77.76 MHz path. (default) 0101: The output of T4 DPLL 12E1/24T1/E3/T3 path. 0110: The output of T4 DPLL 16E1/16T1 path. 0111: The output of T4 DPLL GSM/GPS/16E1/16T1 path. 1XXX: Reserved. These bits select an output clock from the T4 DPLL GSM/GPS/16E1/16T1 path. 00: 16E1. 01: 16T1. T4_GSM_GPS_16E1_16T1_SEL[1:0] 10: GSM. 11: GPS. The default value of the T0_GSM_GPS_16E1_16T1_SEL0 bit is determined by the SONET/SDH pin during reset. These bits select an output clock from the T4 DPLL 12E1/24T1/E3/T3 path. 00: 12E1. 01: 24T1. T4_12E1_24T1_E3_T3_SEL[1:0] 10: E3. 11: T3. The default value of the T4_12E1_24T1_E3_T3_SEL0 bit is determined by the SONET/SDH pin during reset. Programming Information 98 June 19, 2006 IDT82V3255 WAN PLL T4_DPLL_LOCKED_BW_DAMPING_CNFG - T4 DPLL Locked Bandwidth & Damping Factor Configuration Address: 61H Type: Read / Write Default Value: 011XXX00 7 T4_DPLL_LOCK ED_DAMPING2 Bit 6 T4_DPLL_LOCK ED_DAMPING1 Name 5 T4_DPLL_LOCK ED_DAMPING0 4 3 2 Description 1 T4_DPLL_LOC KED_BW1 0 T4_DPLL_LOC KED_BW0 7-5 4-2 1-0 These bits set the locked damping factor for T4 DPLL. 000: Reserved. 001: 1.2. 010: 2.5. T4_DPLL_LOCKED_DAMPING[2:0] 011: 5. (default) 100: 10. 101: 20. 110, 111: Reserved. Reserved. These bits set the locked bandwidth for T4 DPLL. 00: 18 Hz. (default) T4_DPLL_LOCKED_BW[1:0] 01: 35 Hz. 10: 70 Hz. 11: 560 Hz. CURRENT_DPLL_FREQ[7:0]_STS - DPLL Current Frequency Status 1 * Address: 62H Type: Read Default Value: 00000000 7 CURRENT_DP LL_FREQ7 Bit 7-0 6 CURRENT_DP LL_FREQ6 Name 5 CURRENT_DP LL_FREQ5 4 CURRENT_DP LL_FREQ4 3 CURRENT_DP LL_FREQ3 2 CURRENT_DP LL_FREQ2 Description 1 CURRENT_DP LL_FREQ1 0 CURRENT_DP LL_FREQ0 CURRENT_DPLL_FREQ[7:0] Refer to the description of the CURRENT_DPLL_FREQ[23:16] bits (b7~0, 64H). CURRENT_DPLL_FREQ[15:8]_STS - DPLL Current Frequency Status 2 * Address: 63H Type: Read Default Value: 00000000 7 CURRENT_DP LL_FREQ15 Bit 7-0 6 CURRENT_DP LL_FREQ14 Name 5 CURRENT_DP LL_FREQ13 4 CURRENT_DP LL_FREQ12 3 CURRENT_DP LL_FREQ11 2 CURRENT_DP LL_FREQ10 Description 1 CURRENT_DP LL_FREQ9 0 CURRENT_DP LL_FREQ8 CURRENT_DPLL_FREQ[15:8] Refer to the description of the CURRENT_DPLL_FREQ[23:16] bits (b7~0, 64H). Programming Information 99 June 19, 2006 IDT82V3255 WAN PLL CURRENT_DPLL_FREQ[23:16]_STS - DPLL Current Frequency Status 3 * Address: 64H Type: Read Default Value: 00000000 7 CURRENT_DP LL_FREQ23 Bit 7-0 6 CURRENT_DP LL_FREQ22 Name 5 CURRENT_DP LL_FREQ21 4 CURRENT_DP LL_FREQ20 3 CURRENT_DP LL_FREQ19 2 CURRENT_DP LL_FREQ18 Description 1 CURRENT_DP LL_FREQ17 0 CURRENT_DP LL_FREQ16 The CURRENT_DPLL_FREQ[23:0] bits represent a 2's complement signed integer. If the value in these bits is mulCURRENT_DPLL_FREQ[23:16] tiplied by 0.000011, the current frequency offset of the T0/T4 DPLL output in ppm with respect to the master clock will be gotten. DPLL_FREQ_SOFT_LIMIT_CNFG - DPLL Soft Limit Configuration Address: 65H Type: Read / Write Default Value: 10001100 7 FREQ_LIMT_P H_LOS Bit 7 6 DPLL_FREQ_S OFT_LIMT6 Name FREQ_LIMT_PH_LOS 5 DPLL_FREQ_S OFT_LIMT5 4 DPLL_FREQ_S OFT_LIMT4 3 DPLL_FREQ_S OFT_LIMT3 2 DPLL_FREQ_S OFT_LIMT2 1 DPLL_FREQ_S OFT_LIMT1 0 DPLL_FREQ_S OFT_LIMT0 Description 6-0 This bit determines whether the T0/T4 DPLL in hard alarm status will result in it unlocked. 0: Disabled. 1: Enabled. (default) These bits represent an unsigned integer. If the value is multiplied by 0.724, the DPLL soft limit for T0 and T4 paths in DPLL_FREQ_SOFT_LIMT[6:0] ppm will be gotten. The DPLL soft limit is symmetrical about zero. DPLL_FREQ_HARD_LIMIT[7:0]_CNFG - DPLL Hard Limit Configuration 1 Address: 66H Type: Read / Write Default Value: 10101011 7 DPLL_FREQ_H ARD_LIMT7 Bit 7-0 6 DPLL_FREQ_H ARD_LIMT6 Name 5 DPLL_FREQ_H ARD_LIMT5 4 DPLL_FREQ_H ARD_LIMT4 3 DPLL_FREQ_H ARD_LIMT3 2 DPLL_FREQ_H ARD_LIMT2 Description 1 DPLL_FREQ_H ARD_LIMT1 0 DPLL_FREQ_H ARD_LIMT0 DPLL_FREQ_HARD_LIMT[7:0] Refer to the description of the DPLL_FREQ_HARD_LIMT[15:8] bits (b7~0, 67H). Programming Information 100 June 19, 2006 IDT82V3255 WAN PLL DPLL_FREQ_HARD_LIMIT[15:8]_CNFG - DPLL Hard Limit Configuration 2 Address: 67H Type: Read / Write Default Value: 00011001 7 DPLL_FREQ_H ARD_LIMT15 Bit 7-0 6 DPLL_FREQ_H ARD_LIMT14 Name 5 DPLL_FREQ_H ARD_LIMT13 4 DPLL_FREQ_H ARD_LIMT12 3 DPLL_FREQ_H ARD_LIMT11 2 DPLL_FREQ_H ARD_LIMT10 Description 1 DPLL_FREQ_H ARD_LIMT9 0 DPLL_FREQ_H ARD_LIMT8 The DPLL_FREQ_HARD_LIMT[15:0] bits represent an unsigned integer. If the value is multiplied by 0.0014, the DPLL_FREQ_HARD_LIMT[15:8] DPLL hard limit for T0 and T4 paths in ppm will be gotten. The DPLL hard limit is symmetrical about zero. CURRENT_DPLL_PHASE[7:0]_STS - DPLL Current Phase Status 1 * Address: 68H Type: Read Default Value: 00000000 7 CURRENT_PH _DATA7 Bit 7-0 6 CURRENT_PH _DATA6 Name 5 CURRENT_PH _DATA5 4 CURRENT_PH _DATA4 3 CURRENT_PH _DATA3 2 CURRENT_PH _DATA2 Description 1 CURRENT_PH _DATA1 0 CURRENT_PH _DATA0 CURRENT_PH_DATA[7:0] Refer to the description of the CURRENT_PH_DATA[15:8] bits (b7~0, 69H). CURRENT_DPLL_PHASE[15:8]_STS - DPLL Current Phase Status 2 * Address: 69H Type: Read Default Value: 00000000 7 CURRENT_PH _DATA15 Bit 7-0 6 CURRENT_PH _DATA14 Name 5 CURRENT_PH _DATA13 4 CURRENT_PH _DATA12 3 CURRENT_PH _DATA11 2 CURRENT_PH _DATA10 Description 1 CURRENT_PH _DATA9 0 CURRENT_PH _DATA8 The CURRENT_PH_DATA[15:0] bits represent a 2's complement signed integer. If the value is multiplied by 0.61, the CURRENT_PH_DATA[15:8] averaged phase error of the T0/T4 DPLL feedback with respect to the selected input clock in ns will be gotten. Programming Information 101 June 19, 2006 IDT82V3255 WAN PLL T0_T4_APLL_BW_CNFG - T0 / T4 APLL Bandwidth Configuration Address: 6AH Type: Read / Write Default Value: XX01XX01 7 Bit 7-6 Name Reserved. These bits set the bandwidth for T0 APLL. 00: 100 kHz. T0_APLL_BW[1:0] 01: 500 kHz. (default) 10: 1 MHz. 11: 2 MHz. Reserved. These bits set the bandwidth for T4 APLL. 00: 100 kHz. T4_APLL_BW[1:0] 01: 500 kHz. (default) 10: 1 MHz. 11: 2 MHz. 6 5 T0_APLL_BW1 4 T0_APLL_BW0 3 Description 2 1 T4_APLL_BW1 0 T4_APLL_BW0 5-4 3-2 1-0 Programming Information 102 June 19, 2006 IDT82V3255 WAN PLL 6.2.8 OUTPUT CONFIGURATION REGISTERS OUT2_FREQ_CNFG - Output Clock 2 Frequency Configuration Address: 6DH Type: Read / Write Default Value: 00001000 7 OUT2_PATH_S EL3 Bit 6 OUT2_PATH_S EL2 Name 5 OUT2_PATH_S EL1 4 OUT2_PATH_S EL0 3 OUT2_DIVIDER 3 2 OUT2_DIVIDER 2 1 OUT2_DIVIDER 1 0 OUT2_DIVIDER 0 Description 7-4 3-0 These bits select an input to OUT2. 0000 ~ 0011: The output of T0 APLL. (default: 0000) 0100: The output of T0 DPLL 77.76 MHz path. 0101: The output of T0 DPLL 12E1/24T1/E3/T3 path. 0110: The output of T0 DPLL 16E1/16T1 path. OUT2_PATH_SEL[3:0] 0111: The output of T0 DPLL GSM/OBSAI/16E1/16T1 path. 1000 ~ 1011: The output of T4 APLL. 1100: The output of T4 DPLL 77.76 MHz path. 1101: The output of T4 DPLL 12E1/24T1/E3/T3 path. 1110: The output of T4 DPLL 16E1/16T1 path. 1111: The output of T4 DPLL GSM/GPS/16E1/16T1 path. These bits select a division factor of the divider for OUT2. The output frequency is determined by the division factor and the signal derived from T0/T4 DPLL or T0/T4 APLL output OUT2_DIVIDER[3:0] (selected by the OUT2_PATH_SEL[3:0] bits (b7~4, 6DH)). If the signal is derived from one of the T0/T4 DPLL outputs, please refer to Table 25 for the division factor selection. If the signal is derived from the T0/T4 APLL output, please refer to Table 26 for the division factor selection. Programming Information 103 June 19, 2006 IDT82V3255 WAN PLL OUT1_FREQ_CNFG - Output Clock 1 Frequency Configuration Address:71H Type: Read / Write Default Value: 00001000 7 OUT1_PATH_S EL3 Bit 6 OUT1_PATH_S EL2 Name 5 OUT1_PATH_S EL1 4 OUT1_PATH_S EL0 3 OUT1_DIVIDER 3 2 OUT1_DIVIDER 2 1 OUT1_DIVIDER 1 0 OUT1_DIVIDER 0 Description 7-4 3-0 These bits select an input to OUT1. 0000 ~ 0011: The output of T0 APLL. (default: 0000) 0100: The output of T0 DPLL 77.76 MHz path. 0101: The output of T0 DPLL 12E1/24T1/E3/T3 path. 0110: The output of T0 DPLL 16E1/16T1 path. OUT1_PATH_SEL[3:0] 0111: The output of T0 DPLL GSM/OBSAI/16E1/16T1 path. 1000 ~ 1011: The output of T4 APLL. 1100: The output of T4 DPLL 77.76 MHz path. 1101: The output of T4 DPLL 12E1/24T1/E3/T3 path. 1110: The output of T4 DPLL 16E1/16T1 path. 1111: The output of T4 DPLL GSM/GPS/16E1/16T1 path. These bits select a division factor of the divider for OUT1. The output frequency is determined by the division factor and the signal derived from T0/T4 DPLL or T0/T4 APLL output OUT1_DIVIDER[3:0] (selected by the OUT1_PATH_SEL[3:0] bits (b7~4, 71H)). If the signal is derived from one of the T0/T4 DPLL outputs, please refer to Table 25 for the division factor selection. If the signal is derived from the T0/T4 APLL output, please refer to Table 26 for the division factor selection. OUT1_INV_CNFG - Output Clock 1 Invert Configuration Address:72H Type: Read / Write Default Value: XXXXXX0X 7 6 5 4 3 2 1 OUT1_INV 0 - Bit 7-2 1 0 Name OUT1_INV - Description Reserved. This bit determines whether the output on OUT1 is inverted. 0: Not inverted. (default) 1: Inverted. Reserved. Programming Information 104 June 19, 2006 IDT82V3255 WAN PLL OUT2_INV_CNFG - Output Clock 2 Invert Configuration Address:73H Type: Read / Write Default Value: XXXXX0XX 7 6 5 4 3 2 OUT2_INV 1 0 - Bit 7-3 2 1-0 Name OUT2_INV - Description Reserved. This bit determines whether the output on OUT2 is inverted. 0: Not inverted. (default) 1: Inverted. Reserved. Programming Information 105 June 19, 2006 IDT82V3255 WAN PLL FR_MFR_SYNC_CNFG - Frame Sync & Multiframe Sync Output Configuration Address:74H Type: Read / Write Default Value: 01100000 7 IN_2K_4K_8K_I NV Bit 7 6 8K_EN Name 5 2K_EN 4 2K_8K_PUL_P OSITION 3 8K_INV 2 8K_PUL Description 1 2K_INV 0 2K_PUL 6 5 4 3 2 1 0 This bit determines whether the input clock is inverted before locked by the T0/T4 DPLL when the input clock is 2 kHz, 4 kHz or 8 kHz. IN_2K_4K_8K_INV 0: Not inverted. (default) 1: Inverted. This bit determines whether an 8 kHz signal is enabled to be output on FRSYNC_8K. 8K_EN 0: Disabled. FRSYNC_8K outputs low. 1: Enabled. (default) This bit determines whether a 2 kHz signal is enabled to be output on MFRSYNC_2K. 2K_EN 0: Disabled. MFRSYNC_2K outputs low. 1: Enabled. (default) This bit is valid only when FRSYNC_8K and/or MFRSYNC_2K output pulse; i.e., when one of the 8K_PUL bit (b2, 74H) and the 2K_PUL bit (b0, 74H) is `1' or when the 8K_PUL bit (b2, 74H) and the 2K_PUL bit (b0, 74H) are both `1'. It deter2K_8K_PUL_POSITION mines the pulse position referring to the standard 50:50 duty cycle. 0: Pulsed on the falling edge of the standard 50:50 duty cycle position. (default) 1: Pulsed on the rising edge of the standard 50:50 duty cycle position. This bit determines whether the output on FRSYNC_8K is inverted. 8K_INV 0: Not inverted. (default) 1: Inverted. This bit determines whether the output on FRSYNC_8K is 50:50 duty cycle or pulsed. 8K_PUL 0: 50:50 duty cycle. (default) 1: Pulsed. The pulse width is defined by the period of the output on OUT2. This bit determines whether the output on MFRSYNC_2K is inverted. 2K_INV 0: Not inverted. (default) 1: Inverted. This bit determines whether the output on MFRSYNC_2K is 50:50 duty cycle or pulsed. 2K_PUL 0: 50:50 duty cycle. (default) 1: Pulsed. The pulse width is defined by the period of the output on OUT2. Programming Information 106 June 19, 2006 IDT82V3255 WAN PLL 6.2.9 PBO & PHASE OFFSET CONTROL REGISTERS PHASE_MON_PBO_CNFG - Phase Transient Monitor & PBO Configuration Address:78H Type: Read / Write Default Value: 0X000110 7 IN_NOISE_WIN DOW Bit 7 6 5 6 Name 5 PH_MON_EN 4 PH_MON_PBO _EN 3 PH_TR_MON_L IMT3 2 PH_TR_MON_L IMT2 1 PH_TR_MON_L IMT1 0 PH_TR_MON_L IMT0 Description 4 3-0 This bit determines whether the input clock whose edge respect to the reference clock is outside 5% is enabled to be selected for T0/T4 DPLL. IN_NOISE_WINDOW 0: Disabled. (default) 1: Enabled. Reserved. This bit is valid only when the PH_MON_PBO_EN bit (b4, 78H) is `1'. It determines whether the Phase Transient Monitor is enabled to monitor the phase-time changes on the T0 selected input clock. PH_MON_EN 0: Disabled. (default) 1: Enabled. This bit determines whether a PBO event is triggered when the phase-time changes on the T0 selected input clock are greater than a programmable limit over an interval of less than 0.1 seconds with the PH_MON_EN bit being `1'. The limit PH_MON_PBO_EN is programmed by the PH_TR_MON_LIMT[3:0] bits (b3~0, 78H). 0: Disabled. (default) 1: Enabled. These bits represent an unsigned integer. The Phase Transient Monitor limit in ns can be calculated as follows: PH_TR_MON_LIMT[3:0] Limit (ns) = (PH_TR_MON_LIMT[3:0] + 7) X 156. PHASE_OFFSET[7:0]_CNFG - Phase Offset Configuration 1 Address:7AH Type: Read / Write Default Value: 00000000 7 PH_OFFSET7 Bit 7-0 6 PH_OFFSET6 Name 5 PH_OFFSET5 4 PH_OFFSET4 3 PH_OFFSET3 2 PH_OFFSET2 1 PH_OFFSET1 0 PH_OFFSET0 Description PH_OFFSET[7:0] Refer to the description of the PH_OFFSET[9:8] bits (b1~0, 7BH). Programming Information 107 June 19, 2006 IDT82V3255 WAN PLL PHASE_OFFSET[9:8]_CNFG - Phase Offset Configuration 2 Address:7BH Type: Read / Write Default Value: 0XXXXX00 7 PH_OFFSET_E N Bit 7 6-2 1-0 Name 6 5 4 3 2 1 PH_OFFSET9 0 PH_OFFSET8 Description This bit determines whether the input-to-output phase offset is enabled. PH_OFFSET_EN 0: Disabled. (default) 1: Enabled. Reserved. These bits represent a 2's complement signed integer. If the value is multiplied by 0.61, the input-to-output phase offset in ns PH_OFFSET[9:8] to adjust will be gotten. Programming Information 108 June 19, 2006 IDT82V3255 WAN PLL 6.2.10 SYNCHRONIZATION CONFIGURATION REGISTERS SYNC_MONITOR_CNFG - Sync Monitor Configuration Address:7CH Type: Read / Write Default Value: 00101011 7 SYNC_BYPASS Bit 6 SYNC_MON_LIMT2 Name 5 SYNC_MON_LIMT1 4 SYNC_MON_LIMT0 3 Description 2 1 0 - 7 6-4 3-0 This bit selects one frame sync input signal to synchronize the frame sync output signals. 0: EX_SYNC1 is selected. (default) SYNC_BYPASS 1: When the T0 selected input clock is IN1_CMOS or IN1_DIFF, EX_SYNC1 is selected; when the T0 selected input clock is IN2_CMOS or IN2_DIFF, EX_SYNC2 is selected; when the T0 selected input clock is IN3_CMOS, EX_SYNC3 is selected; when there is no T0 selected input clock, no frame sync input signal is selected. These bits set the limit for the external sync alarm. 000: 1 UI. 001: 2 UI. 010: 3 UI. (default) SYNC_MON_LIMT[2:0] 011: 4 UI. 100: 5 UI. 101: 6 UI. 110: 7 UI. 111: 8 UI. These bits must be set to `1011'. Programming Information 109 June 19, 2006 IDT82V3255 WAN PLL SYNC_PHASE_CNFG - Sync Phase Configuration Address:7DH Type: Read / Write Default Value: XX000000 7 Bit 7-6 Name 6 5 SYNC_PH31 4 SYNC_PH30 3 SYNC_PH21 2 SYNC_PH20 1 SYNC_PH11 0 SYNC_PH10 Description Reserved. These bits set the sampling of EX_SYNC3 when EX_SYNC3 is enabled to synchronize the frame sync output signal. Nominally, the falling edge of EX_SYNC3 is aligned with the rising edge of the T0 selected input clock. 00: On target. (default) 01: 0.5 UI early. 10: 1 UI late. 11: 0.5 UI late. These bits set the sampling of EX_SYNC2 when EX_SYNC2 is enabled to synchronize the frame sync output signal. Nominally, the falling edge of EX_SYNC2 is aligned with the rising edge of the T0 selected input clock. 00: On target. (default) 01: 0.5 UI early. 10: 1 UI late. 11: 0.5 UI late. These bits set the sampling of EX_SYNC1 when EX_SYNC1 is enabled to synchronize the frame sync output signal. Nominally, the falling edge of EX_SYNC1 is aligned with the rising edge of the T0 selected input clock. 00: On target. (default) 01: 0.5 UI early. 10: 1 UI late. 11: 0.5 UI late. 5-4 SYNC_PH3[1:0] 3-2 SYNC_PH2[1:0] 1-0 SYNC_PH1[1:0] Programming Information 110 June 19, 2006 IDT82V3255 WAN PLL 7 THERMAL MANAGEMENT The device operates over the industry temperature range -40C ~ +85C. To ensure the functionality and reliability of the device, the maximum junction temperature Tjmax should not exceed 125C. In some applications, the device will consume more power and a thermal solution should be provided to ensure the junction temperature Tj does not exceed the Tjmax. The junction temperature Tj can be calculated as follows: Tj = TA + P X JA = 85C + 1.57W X 18.8C/W = 114.5C The junction temperature of 114.5C is below the maximum junction temperature of 125C so no extra heat enhancement is required. In some operation environments, the calculated junction temperature might exceed the maximum junction temperature of 125C and an external thermal solution such as a heatsink is required. 7.1 JUNCTION TEMPERATURE 7.3 HEATSINK EVALUATION Junction temperature Tj is the temperature of package typically at the geographical center of the chip where the device's electrical circuits are. It can be calculated as follows: Equation 1: Tj = TA + P X JA Where: JA = Junction-to-Ambient Thermal Resistance of the Package Tj = Junction Temperature TA = Ambient Temperature P = Device Power Consumption A heatsink is expanding the surface area of the device to which it is attached. JA is now a combination of device case and heat-sink thermal resistance, as the heat flowing from the die junction to ambient goes through the package and the heatsink. JA can be calculated as follows: Equation 2: JA = JC + HA Where: JC = Junction-to-Case (Heatsink) Thermal Resistance HA = Heatsink-to-Ambient Thermal Resistance HA determines which heatsink can be selected to ensure the junction temperature does not exceed the maximum junction temperature. According to Equation 1 and 2, the heatsink-to-ambient thermal resistance HA can be calculated as follows: Equation 3: HA = (Tj - TA) / P - JC Assume: Tj = 125C (Tjmax) TA = 85C P = 1.57W In order to calculate junction temperature, an appropriate JA must be used. The JA is shown in Table 36: Power consumption is the core power excluding the power dissipated in the loads. Table 35 provides power consumption in special environments. Table 35: Power Consumption and Maximum Junction Temperature Package TQFP/PP64 TQFP/DK64 Power Consumption (W) 1.57 1.57 Operating Voltage (V) 3.6 3.6 Maximum TA (C) Junction Temperature (C) 85 85 125 125 JC = 11.9C/W (TQFP/DK64) The heatsink-to-ambient thermal resistance HA can be calculated as follows: HA = (125C - 85C ) / 1.57W - 11.9C/W = 13.6C/W That is, if a heatsink whose heatsink-to-ambient thermal resistance HA is below or equal to 13.6C/W is used in such operation environment, the junction temperature will not exceed the maximum junction temperature. 7.2 EXAMPLE OF JUNCTION TEMPERATURE CALCULATION TA = 85C Assume: JA = 18.8C/W (TQFP/DK64 Soldered & when airfow rate is 0 m/s) P = 1.57W Table 36: Thermal Data Package TQFP/PP64 TQFP/DK64 TQFP/DK64 Pin Count 64 64 64 Thermal Pad No Yes/Exposed Yes/Soldered JC (C/W) 12.3 11.9 11.9 JB (C/W) 35.1 24.9 3.2 JA (C/W) Air Flow in m/s 0 43.1 32.6 18.8 1 40 29.7 15.7 2 38.1 27.8 14.3 3 37.3 26.9 13.4 4 36.5 26 12.8 5 36.1 25.5 12.5 Thermal Management 111 June 19, 2006 IDT82V3255 WAN PLL 8 8.1 ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATING Table 37: Absolute Maximum Rating Symbol VDD VIN VOUT TA TSTOR Parameter Supply Voltage VDD Input Voltage (non-supply pins) Output Voltage (non-supply pins) Ambient Operating Temperature Range Storage Temperature -40 -50 Min -0.5 Max 3.6 5.5 5.5 +85 +150 Unit V V V C C 8.2 RECOMMENDED OPERATION CONDITIONS Table 38: Recommended Operation Conditions Symbol VDD TA IDD PTOT Parameter Power Supply (DC voltage) VDD Ambient Temperature Range Supply Current Total Power Dissipation Min 3.0 -40 388 1.28 Typ 3.3 Max 3.6 +85 436 1.57 Unit V C mA W Electrical Specifications 112 June 19, 2006 IDT82V3255 WAN PLL 8.3 8.3.1 I/O SPECIFICATIONS CMOS INPUT / OUTPUT PORT From Table 39 to Table 42, VDD is 3.3 V. Table 39: CMOS Input Port Electrical Characteristics Parameter VIH VIL IIN VIN Description Input Voltage High Input Voltage Low Input Current Input Voltage -0.5 Min 0.7VDD 0.2VDD 10 5.5 Typ Max Unit V V A V Test Condition Table 40: CMOS Input Port with Internal Pull-Up Resistor Electrical Characteristics Parameter VIH VIL PU IIN VIN Description Input Voltage High Input Voltage Low Pull-Up Resistor Input Current Input Voltage -0.5 10 Min 0.7VDD 0.2VDD 80 250 5.5 Typ Max Unit V V K A V Test Condition Table 41: CMOS Input Port with Internal Pull-Down Resistor Electrical Characteristics Parameter VIH VIL PD Description Input Voltage High Input Voltage Low Pull-Down Resistor 10 5 100 Min 0.7VDD 0.2VDD 80 40 300 350 700 40 5.5 Typ Max Unit V V K other CMOS input port with internal pull-down resistor TRST and TCK pin SDI, CLKE pin other CMOS input port with internal pull-down resistor TRST and TCK pin SDI, CLKE pin Test Condition IIN VIN Input Current Input Voltage -0.5 A V Table 42: CMOS Output Port Electrical Characteristics Application Pin Parameter VOH Output Clock VOL tR tF VOH Other Output VOL tR tF Description Output Voltage High Output Voltage Low Rise time Fall time Output Voltage High Output Voltage Low Rise Time Fall Time 2.5 0 Min 2.4 0 3 3 Typ Max VDD 0.4 4 4 VDD 0.4 10 10 Unit V V ns ns V V ns ns Test Condition IOH = 8 mA IOL = 8 mA 15 pF 15 pF IOH = 4 mA IOL= 4 mA 50 pF 50 pF Electrical Specifications 113 June 19, 2006 IDT82V3255 WAN PLL 8.3.2 8.3.2.1 PECL / LVDS INPUT / OUTPUT PORT PECL Input / Output Port VDD (+ 3.3 V) 130 50 (transmission line) 2 kHz to 667 MHz 82 GND VDD (+ 3.3 V) 130 IN1_NEG 82 GND VDD (+ 3.3 V) 50 (transmission line) 130 IN2_POS 82 2 kHz to 667 MHz GND VDD (+ 3.3 V) IN2_NEG IN1_POS 130 82 VDD (+ 3.3 V) GND 50 (transmission line) 2 kHz OUT1_POS to 667 MHz OUT1_NEG 50 (transmission line) VDD (+ 3.3 V) GND 130 82 50 (transmission line) Figure 19. Recommended PECL Output Port Line Termination 130 50 (transmission line) 82 GND Figure 18. Recommended PECL Input Port Line Termination Electrical Specifications 114 June 19, 2006 IDT82V3255 WAN PLL Table 43: PECL Input / Output Port Electrical Characteristics Parameter VIL VIH VID VIL_S VIH_S IIH IIL VOL VOH VOD tRISE tFALL tSKEW Description Input Low Voltage, Differential Inputs Input Differential Voltage Input Low Voltage, Single-ended Input 2 Input High Voltage, Single-ended Input 2 Input High Current, Input Differential Voltage VID = 1.4 V Input Low Current, Input Differential Voltage VID = 1.4 V Output Voltage Low 3 Output Voltage High 3 Output Differential Voltage3 Output Rise time (20% to 80%) Output Fall time (20% to 80%) Output Differential Skew 1 Min VDD - 2.5 VDD - 2.4 0.1 VDD - 2.4 VDD - 1.3 -10 -10 VDD - 2.1 VDD - 1.25 580 200 200 Typ Max VDD - 0.5 VDD - 0.4 1.4 VDD - 1.5 VDD - 0.5 10 10 VDD - 1.62 VDD - 0.88 900 300 300 50 Unit V V V V V A A V V mV pS pS pS Test Condition Input High Voltage, Differential Inputs 1 Note: 1. Assuming a differential input voltage of at least 100 mV. 2. Unused differential input terminated to VDD-1.4 V. 3. With 50 load on each pin to VDD-2 V, i.e. 82 to GND and 130 to VDD. Electrical Specifications 115 June 19, 2006 IDT82V3255 WAN PLL 8.3.2.2 LVDS Input / Output Port 50 (transmission line) 100 50 (transmission line) IN1_NEG OUT1_POS IN1_POS 50 (transmission line) 100 2 kHz to 667 MHz OUT1_NEG 50 (transmission line) 2 kHz to 667 MHz 50 (transmission line) IN2_POS 2 kHz to 100 667 MHz IN2_NEG 50 (transmission line) Figure 21. Recommended LVDS Output Port Line Termination Figure 20. Recommended LVDS Input Port Line Termination Table 44: LVDS Input / Output Port Electrical Characteristics Parameter Description Min Typ Max Unit Test Condition VCM VDIFF VIDTH RTERM VOH VOL VOD VOS RO RO VOD VOS ISA, ISB ISAB tRISE tFALL tSKEW Input Common-mode Voltage Range Input Peak Differential Voltage Input Differential Threshold External Differential Termination Impedance Output Voltage High Output Voltage Low Differential Output Voltage Output Offset Voltage Differential Output Impedance RO Mismatch between A and B Change in VOD between Logic 0 and Logic 1 Change in VOS between Logic 0 and Logic 1 Output Current Output Current Output Rise time (20% to 80%) Output Fall time (20% to 80%) Output Differential Skew 0 100 -100 95 1350 925 250 1125 80 1200 2400 900 100 mV mV mV mV mV mV mV % mV mV mA mA pS pS pS RLOAD = 100 1% RLOAD = 100 1% RLOAD = 100 1% RLOAD = 100 1% VCM = 1.0 V or 1.4 V VCM = 1.0 V or 1.4 V RLOAD = 100 1% RLOAD = 100 1% Driver shorted to GND Driver shorted together RLOAD = 100 1% RLOAD = 100 1% RLOAD = 100 1% 100 105 1475 1100 400 1275 100 120 20 25 25 24 12 200 200 300 300 50 Electrical Specifications 116 June 19, 2006 IDT82V3255 WAN PLL 8.4 JITTER & WANDER PERFORMANCE Table 45: Output Clock Jitter Generation Test Definition 1 Peak to Peak Typ RMS Typ Note Test Filter N x 2.048MHz without APLL N x 2.048MHz with T0/T4 APLL N x 1.544 MHz without APLL N x 1.544 MHz with T0/T4 APLL 44.736 MHz without APLL 44.736 MHz with T0/T4 APLL 34.368 MHz without APLL 34.368 MHz with T0/T4 APLL <2 ns <1 ns <2 ns <1 ns <1 ns <2 ns <1 ns <2 ns <200 ps <100 ps <200 ps <100 ps <100 ps <200 ps <100 ps <200 ps See Table 46: Output Clock Phase Noise for details See Table 46: Output Clock Phase Noise for details See Table 46: Output Clock Phase Noise for details See Table 46: Output Clock Phase Noise for details GR-253, G.813 Option 2 limit 0.1 UI p-p (1 UI-6430 ps) G.813 Option 1, G.812 limit 0.5 UI p-p (1 UI-6430 ps) G.813 Option 1 limit 0.1 UI p-p (1 UI-6430 ps) GR-253, G.813 Option 2 limit 0.1 UI p-p (1 UI-1608 ps) G.813 Option 1, G.812 limit 0.5 UI p-p (1 UI-1608 ps) G.813 Option 1, G.812 limit 0.1 UI p-p (1 UI-160 8ps) G.813 Option 1, G.812 limit 0.5 UI p-p (1 UI-402 ps) G.813 Option 1, G.812 limit 0.1 UI p-p (1 UI-402 ps) 20 Hz - 100 kHz 20 Hz - 100 kHz 10 Hz - 40 kHz 10 Hz - 40 kHz 100 Hz - 800 kHz 100 Hz - 800 kHz 10 Hz - 400 kHz 10 Hz - 400 kHz 12 kHz - 1.3 MHz 0.004 UI p-p 0.001 UI RMS OC-3 (Chip T0 DPLL + T0/T4 APLL) 6.48 MHz, 19.44 MHz, 25.92 0.004 UI p-p 0.001 UI RMS MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz, 155.52 MHz, 311.04 MHz, 622.08 MHz output 0.001 UI p-p 0.001 UI RMS 500 Hz - 1.3 MHz 65 kHz - 1.3 MHz 0.018 UI p-p 0.007 UI RMS OC-12 (Chip T0 DPLL + T0/T4 APLL) 6.48 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz, 155.52 MHz, 0.028 UI p-p 0.009 UI RMS 311.04 MHz, 622.08 MHz output + Intel GD16523 + Optical transceiver) 0.002 UI p-p 0.001 UI RMS STM-16 0.162 UI p-p 0.03 UI RMS (Chip T0 DPLL + T0/T4 APLL) 6.48 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz, 155.52 MHz, 311.04 MHz, 622.08 MHz output + Intel GD16523 + Optical 0.01 UI p-p 0.009 UI RMS transceiver) Note: 1. CMAC E2747 TCXO is used. 12 kHz - 5 MHz 1 kHz - 5 MHz 250 kHz - 5 MHz 5 kHz - 20 MHz 1 MHz - 20 MHz Electrical Specifications 117 June 19, 2006 IDT82V3255 WAN PLL Table 46: Output Clock Phase Noise Output Clock 1 @100Hz Offset Typ @1kHz Offset Typ @10kHz Offset @100kHz Offset Typ Typ @1MHz Offset @5MHz Offset Typ Typ Unit 622.08 MHz (T0 DPLL + T0/T4 APLL) 155.52 MHz (T0 DPLL + T0/T4 APLL) 38.88 MHz (T0 DPLL + T0/T4 APLL) 16E1 (T0/T4 APLL) 16T1 (T0/T4 APLL) E3 (T0/T4 APLL) T3 (T0/T4 APLL) Note: 1. CMAC E2747 TCXO is used. -70 -82 -94 -94 -95 -93 -92 -86 -98 -110 -110 -112 -109 -108 -95 -107 -118 -118 -120 -116 -116 -100 -112 -124 -125 -127 -124 -122 -107 -119 -131 -131 -132 -131 -126 -128 -140 -143 -142 -143 -138 -141 dBC/Hz dBC/Hz dBC/Hz dBC/Hz dBC/Hz dBC/Hz dBC/Hz Table 47: Input Jitter Tolerance (155.52 MHz) Jitter Frequency Jitter Tolerance Amplitude (UI p-p) Table 49: Input Jitter Tolerance (2.048 MHz) Jitter Frequency Jitter Tolerance Amplitude (UI p-p) 12 Hz 178 Hz 1.6 mHz 15.6 mHz 0.125 Hz 19.3 Hz 500 Hz 6.5 kHz 65 kHz 1.3 MHz > 2800 > 2800 > 311 > 311 > 39 > 39 > 1.5 > 1.5 > 0.15 > 0.15 1 Hz 5 Hz 20 Hz 300 Hz 400 Hz 700 Hz 2400 Hz 10 kHz 50 kHz 100 kHz 150 140 130 40 33 18 5.5 1.3 0.4 0.4 Table 48: Input Jitter Tolerance (1.544 MHz) Jitter Frequency Jitter Tolerance Amplitude (UI p-p) Table 50: Input Jitter Tolerance (8 kHz) Jitter Frequency Jitter Tolerance Amplitude (UI p-p) 1 Hz 5 Hz 20 Hz 300 Hz 400 Hz 700 Hz 2400 Hz 10 kHz 40 kHz 150 140 130 38 25 15 5 1.2 0.5 1 Hz 5 Hz 20 Hz 300 Hz 400 Hz 700 Hz 2400 Hz 3600 Hz 0.8 0.7 0.6 0.16 0.14 0.07 0.02 0.01 Electrical Specifications 118 June 19, 2006 IDT82V3255 WAN PLL Table 51: T0 DPLL Jitter Transfer & Damping Factor 3 dB Bandwidth Programmable Damping Factor Table 52: T4 DPLL Jitter Transfer & Damping Factor 3 dB Bandwidth Programmable Damping Factor 0.1 Hz 0.3 Hz 0.6 Hz 1.2 Hz 2.5 Hz 4 Hz 8 Hz 18 Hz 35 Hz 70 Hz 560 Hz 1.2, 2.5, 5, 10, 20 1.2, 2.5, 5, 10, 20 1.2, 2.5, 5, 10, 20 1.2, 2.5, 5, 10, 20 1.2, 2.5, 5, 10, 20 1.2, 2.5, 5, 10, 20 1.2, 2.5, 5, 10, 20 1.2, 2.5, 5, 10, 20 1.2, 2.5, 5, 10, 20 1.2, 2.5, 5, 10, 20 1.2, 2.5, 5, 10, 20 18 Hz 35 Hz 70 Hz 560 Hz 1.2, 2.5, 5, 10, 20 1.2, 2.5, 5, 10, 20 1.2, 2.5, 5, 10, 20 1.2, 2.5, 5, 10, 20 Electrical Specifications 119 June 19, 2006 IDT82V3255 WAN PLL 8.5 OUTPUT WANDER GENERATION template template tested result tested result Figure 22. Output Wander Generation Electrical Specifications 120 June 19, 2006 IDT82V3255 WAN PLL 8.6 INPUT / OUTPUT CLOCK TIMING The inputs and outputs are aligned ideally. But due to the circuit delays, there is delay between the inputs and outputs. 8 kHz Input Clock t1 8 kHz Output Clock 6.48 MHz Input Clock 6.48 MHz Output Clock t2 19.44 MHz Input Clock 19.44 MHz Output Clock t3 25.92 MHz Input Clock 25.92 MHz Output Clock t4 38.88 MHz Input Clock 38.88 MHz Output Clock t5 51.84 MHz Input Clock 51.84 MHz Output Clock t6 Figure 23. Input / Output Clock Timing Table 53: Input/Output Clock Timing Symbol Typical Delay 1 (ns) Peak to Peak Delay Variation (ns) t1 t2 t3 t4 t5 t6 4 1 1 2 1.4 3 1.6 1.6 1.6 1.6 1.6 1.6 Note: 1. Typical delay provided as reference only. 2. `Peak to Peak Delay Variation' is the delay variation that is guaranteed not to be exceeded for IN11 in Master/Slave operation. 3. Tested when IN11 is selected. Electrical Specifications 121 June 19, 2006 IDT82V3255 WAN PLL 8.7 OUTPUT CLOCK TIMING MFRSYNC_2K/ FRSYNC_8K N X T1 (1.544 MHz) N X E1 (2.048 MHz) E3 (34.368 MHz) T3 (44.736 MHz) 6.48 MHz 19.44 MHz 25.92 MHz 38.88 MHz 51.84 MHz 77.76 MHz 155.52 MHz 311.04 MHz 622.08 MHz t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 Table 54: Output Clock Timing Symbol Typical Delay (ns) Peak to Peak Delay Variation (ns) t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 0 0 0 0 0 0 0 0 0 0 0 0 0 2 2 2 2 2 2 2 2 2 2 1.5 1.5 (not recommended to use) 1.5 (not recommended to use) Electrical Specifications 122 June 19, 2006 Glossary 3G ADSL AMI APLL ATM BITS CMOS DCO DPLL DSL DSLAM DWDM EPROM GPS GSM IIR IP ISDN JTAG LOS LPF LVDS MTIE MUX OBSAI OC-n ----------------------------------------------------- Third Generation Asymmetric Digital Subscriber Line Alternate Mark Inversion Analog Phase Locked Loop Asynchronous Transfer Mode Building Integrated Timing Supply Complementary Metal-Oxide Semiconductor Digital Controlled Oscillator Digital Phase Locked Loop Digital Subscriber Line Digital Subscriber Line Access MUX Dense Wavelength Division Multiplexing Erasable Programmable Read Only Memory Global Positioning System Global System for Mobile Communications Infinite Impulse Response Internet Protocol Integrated Services Digital Network Joint Test Action Group Loss Of Signal Low Pass Filter Low Voltage Differential Signal Maximum Time Interval Error Multiplexer Open Base Station Architecture Initiative Optical Carried rate, n = 1, 3, 12, 48, 192, 768; 51 Mbit/s, 155 Mbit/s, 622 Mbit/s, 2.5 Gbit/s, 10 Gbit/s, 40 Gbit/s. Glossary 123 June 19, 2006 IDT82V3255 WAN PLL PBO PDH PECL PFD PLL RMS PRS SDH SEC SMC SONET SSU STM TCM-ISDN TDEV UI WLL ----------------------------------- Phase Build-Out Plesiochronous Digital Hierarchy Positive Emitter Coupled Logic Phase & Frequency Detector Phase Locked Loop Root Mean Square Primary Reference Source Synchronous Digital Hierarchy SDH / SONET Equipment Clock SONET Minimum Clock Synchronous Optical Network Synchronization Supply Unit Synchronous Transfer Mode Time Compression Multiplexing Integrated Services Digital Network Time Deviation Unit Interval Wireless Local Loop Glossary 124 June 19, 2006 Index A Averaged Phase Error ........................................................................ 31 Frequency Hard Alarm .................................................................21, 26 Frequency Hard Alarm Threshold ...................................................... 21 B Bandwidths and Damping Factors ..................................................... 31 Acquisition Bandwidth and Damping Factor ............................... 31 Locked Bandwidth and Damping Factor ..................................... 31 Starting Bandwidth and Damping Factor .................................... 31 H Hard Limit ........................................................................................... 24 Holdover Frequency Offset ................................................................ 32 I IIR ...................................................................................................... 32 Input Clock Frequency ....................................................................... 21 Input Clock Selection ......................................................................... 22 Automatic selection ..............................................................23, 26 External Fast selection .........................................................22, 26 Forced selection ...................................................................23, 26 Internal Leaky Bucket Accumulator ................................................... 20 Bucket Size ................................................................................ 20 Decay Rate ................................................................................ 20 Lower Threshold ........................................................................ 20 Upper Threshold ........................................................................ 20 C Calibration .......................................................................................... 17 Coarse Phase Loss ............................................................................ 24 Crystal Oscillator ................................................................................ 17 Current Frequency Offset ................................................................... 31 D DCO ................................................................................................... 31 Division Factor .................................................................................... 19 DPLL Hard Alarm ............................................................................... 24 DPLL Hard Limit ................................................................................. 24 DPLL Operating Mode ................................................................. 31, 32 Free-Run mode ................................................................... 31, 32 Holdover mode .................................................................... 31, 32 Automatic Fast Averaged ................................................... 32 Automatic Instantaneous .................................................... 32 Automatic Slow Averaged .................................................. 32 Manual ................................................................................ 32 Locked mode ....................................................................... 31, 32 Temp-Holdover mode ......................................................... 31 Lost-Phase mode ....................................................................... 31 Pre-Locked mode ....................................................................... 31 Pre-Locked2 mode ..................................................................... 32 DPLL Soft Alarm ................................................................................. 24 DPLL Soft Limit .................................................................................. 24 L Limit ................................................................................................... 34 LPF .................................................................................................... 31 M Master Clock ...................................................................................... 17 Microprocessor Interface ................................................................... 43 N No-activity Alarm ..........................................................................20, 26 P PBO ................................................................................................... 34 PFD .................................................................................................... 31 Phase Lock Alarm ........................................................................25, 26 Phase Offset ...................................................................................... 34 Phase-compared ..........................................................................24, 34 Phase-time ......................................................................................... 34 Pre-Divider ......................................................................................... 19 DivN Divider ............................................................................... 19 E External Sync Alarm ........................................................................... 38 F Fast Loss ............................................................................................ 24 Fine Phase Loss ................................................................................. 24 Index 125 June 19, 2006 IDT82V3255 WAN PLL HF Divider ................................................................................... 19 Lock 8k Divider ........................................................................... 19 Non-Revertive switch ................................................................. 27 Revertive switch ......................................................................... 26 State Machine ..............................................................................28, 30 R Reference Clock ................................................................................. 21 V Validity ............................................................................................... 26 S Selected Input Clock Switch ............................................................... 26 Index 126 June 19, 2006 IDT82V3255 WAN PLL ORDERING INFORMATION IDT XXXXXXX Device Type XX X Process/ Temperature Range Blank Industrial (-40 C to +85 C) TF TFG DK DKG 82V3255 Thin Quad Flatpack (TQFP, PP64) Green Thin Quad Flatpack (TQFP, PPG64) Thermal Enhanced Thin Quad Flatpack, ExposedPadTM (TQFP, DK64) Green Thermal Enhanced Thin Quad Flatpack, ExposedPadTM (TQFP, DKG64) WAN PLL DATASHEET DOCUMENT HISTORY 09/28/2005 pgs. 112. 06/19/2006 pgs. 41 CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 www.idt.com 127 for SALES: 1-800-345-7015 or 408-284-8200 fax: 408-284-2775 for Tech Support: 408-360-1552 email:telecomhelp@idt.com IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. |
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